1 tick delayed task start after portSUPPRESS_TICKS_AND_SLEEP

bernatikv wrote on Thursday, April 20, 2017:

I also looked to nordic “port_cmsis_systick.c” and they enable IRQ only after tick compensation (so their code behave correctly -> same in tickless enabled or disabled). I measured that their compensation time takes only 6us (partially due to the arm is using faster clock 64MHz) but mostly due to the fact they are not dividing. Instead of systick timer they used RTC hardware and it uses prescaler to have 1 counted value same as 1 tick. So if you have free RTC HW in your ARM that has Compare register and Prescaler you can write much faster port than is generic free rtos port. The problem is that generic systick needs division operation which is very slow operation. Also RTC with Compare register does not need to be stopped so other benefit of such approach would be that there is not event small time drift in tickless mode (standard free rtos arm port is stopping for while systick counter which creates small tick drift).

bernatikv wrote on Thursday, April 20, 2017:

Hups I made a mistake in previous measurement of original free rtos port.c. I moved __enable_irq(); at the end of vPortSuppressTicksAndSleep() but just now I noticed that ISR is enetered when portEXIT_CRITICAL(); is called. Therefore I measured too long compensation time (I added time for my long demo ISR). When I put my pin toggle before portEXIT_CRITICAL(); then I see that compensation time is not ~1.5ms but only ~18us!!! Division operation is actually fast it takes only ~2us.
But that means that probably most users would prefer to delay first ISR after sleep by 18us and get consistent behavior in both modes (tickless enabled and disabled). If some user needs ISR to be run very quickly he/she probably would not use tickless mode at the first place anyway - because waking CPU up takes also some time (in my case waking Arm M7 CPU takes 5 us, but for example my nordic chip nRF52832 wakes up from sleep 43us). So back to original statement that port.c shall be changed to compensate tick before ISR is called. Or do you still think that 18us is more important that consistent behavior? (if yes then there is no point in arguing - this is up to everyone taste, just add this weird decision to documentation)

tlafleur wrote on Thursday, April 20, 2017:

If you don’t understand how FreeRTOS work or don’t like the way it works.
You have full source code, make the changes you need and be done with it!!!

~~ _/) _/) _/) ``` _/) ~~

Tom Lafleur

On Thu, Apr 20, 2017 at 7:49 AM, Vit Bernatik bernatikv@users.sf.net
wrote:

I also looked to nordic “port_cmsis_systick.c” and they enable IRQ only
after tick compensation (so their code behave correctly → same in tickless
enabled or disabled). I measured that their compensation time takes only
6us (partially due to the arm is using faster clock 64MHz) but mostly due
to the fact they are not dividing. Instead of systick timer they used RTC
hardware and it uses prescaler to have 1 counted value same as 1 tick. So
if you have free RTC HW in your ARM that has Compare register and Prescaler
you can write much faster port than is generic free rtos port. The problem
is that generic systick needs division operation which is very slow
operation. Also RTC with Compare register does not need to be stopped so
other benefit of such approach would be that there is not event small time
drift in tickless mode (standard free rtos arm port is stopping for while
systick counter which creates small tick drift).

1 tick delayed task start after portSUPPRESS_TICKS_AND_SLEEP
https://sourceforge.net/p/freertos/discussion/382005/thread/237a82ca/?limit=25#47f0

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