Zynq Ethernet interrupt targeted at wrong CPU

hannes23 wrote on Thursday, November 14, 2019:


I’ve setup a an AMP project with a Zynq.
The Ethernet controller should be controlled by CPU 1.
But after initialisation the interrupt of the ethernet controller in the PS is generated at CPU 0 instead.

I use the ‘USE_AMP’ switch.

What did I miss to correctly target the Ethernet interrupt to CPU 1?
I think in the end the ICDIPTR 13 register has to be setup accordingly. But where is this done?


rtel wrote on Thursday, November 14, 2019:

I think the USE_AMP switch comes from Xilinx code rather than one of our
projects? Would suggest posting to the Xilinx forum as there will be a
lot more experts on their dual core schemes there.

hannes23 wrote on Thursday, November 14, 2019:

USE_AMP comes from Xilinx, that’s right. It’s supposed to prohibit extra initialisation of some resources, which only CPU 0 should control, like interrupt controller or 2nd-level-cache.

The interesting part is in the file xscugic_hw.c where the distributer-routine is not exectuted by CPU1.

Here a snip of the listing:

static void DistInit(XScuGic_Config *Config, u32 CpuID)
u32 Int_Id;
u32 LocalCpuID = CpuID;

#if USE_AMP == 1
#warning “Building GIC for AMP”

 * The distrubutor should not be initialized by FreeRTOS in the case of
 * AMP -- it is assumed that Linux is the master of this device in that
 * case.


XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);

This is correct on first thought. But if, as in my case the Ethernet interrupt should be targeted to CPU 1, the corresponding distribution register should be corrected.
My guess is to do this somewhere in the routine xNetworkInterfaceInitialise().