For cortex M3/M4, taskENTER_CRITICAL/taskEXIT_CRITICAL mantain a global variable uxCriticalNesting to enable nest, and portSETINTERRUPTMASKFROMISR() - which returns the existing interrupt mask before setting the mask up, and portCLEARINTERRUPTMASKFROMISR() which sets the mask back to its previous value.
I have known that we need to use taskENTER_CRITICAL/taskEXIT_CRITICAL in tasks, and use portSETINTERRUPTMASKFROMISR/portCLEARINTERRUPTMASKFROMISR in ISRs. But why? why I can’t use taskENTER_CRITICAL/taskEXIT_CRITICAL in ISR? If I do, what will be happened?
I have mentioned that because of a combination of the way the port works and the intelligence built into the NVIC it is probably ok to use taskENTER_CRITICAL/taskEXIT_CRITICAL in ISRs. It means specifically only to the Cortex-M3/4 ports, it will be ok, but I don’t know why other core architecture will be not allowed.