Understanding priority levels of ISR and FreeRTOS APIs

[rtel (Richard Barry)]

@MasterSil

sorry but how does having an interrupt of a logically higher priority than configMAX_SYSCALL_INTERRUPT_PRIORITY corrupt the critical sections?

As per:

@rtel

On the Cortex-M FreeRTOS creates critical sections by masking interrupts up to the application writer defined maximum syscall interrupt priority.

That means an interrupt cannot itself be interrupted by another interrupt that has a logical priority below the maximum syscall interrupt priority - and can therefore access whatever is being protected by the critical section.

@MasterSil

Is the logic that you don’t want to interrupt the processor while a critical section is being executed hence why the kernel disables the interrupts?

Yes.

@MasterSil

And I see NVIC_SetPriority() does some bit shift but not sure why ucCurrentPriority is even 0

The priority registers is only 8-bits and will only implement a few bits of the 8-bit register, so presumably when the value gets shifted you are not ending up with any bits set in any of the bits implemented by the hardware, so the value will appear to the hardware as 0. However you have the code there so you can determine exactly what it is doing.