# The SiFive RISC-V port of FreeRTOS **URL:** \ **Category:** SiFive\ **Created:** [May 1, 2022, 6:47am UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960 "2022-05-01T06:47:17Z")\ **Posts on this page:** 12\ **Page:** 1
**Author:** ![stawhite2002](https://avatars.discourse-cdn.com/v4/letter/s/258eb7/32.png) [@stawhite2002](https://forums.freertos.org/u/stawhite2002)\ **Post date:** [May 1, 2022, 6:47am UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/1 "2022-05-01T06:47:17Z")
Has anyone worked with this port? The code that is listed in the download for this port (presumably common demo code) is OK, but opening the demo project itself displays many unexplained directories that seem to be Microchip fpga, mpfs, or PolarFire code that isn’t documented at all and results in hundreds of build errors for the project (mostly multiple variable definitions, incorrect paths for headers, etc.). I thought these demo projects were supposed to build correctly out-of-the-box? ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [May 1, 2022, 5:39pm UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/2 "2022-05-01T17:39:29Z")
Are you building the PolarFire project, or one of the other SiFive projects? ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [May 1, 2022, 5:43pm UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/3 "2022-05-01T17:43:37Z")
Grateful if you can link to the documentation page on [freertos.org](http://freertos.org) for the demo you are building so I can try building too. ---
**Author:** ![stawhite2002](https://avatars.discourse-cdn.com/v4/letter/s/258eb7/32.png) [@stawhite2002](https://forums.freertos.org/u/stawhite2002)\ **Post date:** [May 2, 2022, 5:48am UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/4 "2022-05-02T05:48:04Z")
It’s the ‘RISC-V\_RV32\_SiFive\_HiFive1-RevB\_FreedomStudio’ project, although I’m using the SoftConsole IDE (also Eclipse-based). ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [May 2, 2022, 3:33pm UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/5 "2022-05-02T15:33:40Z")
> [@stawhite2002](#): > > although I’m using the SoftConsole IDE I suspect that is your problem then. It is a SiFive FreedomStudio project, that doesn’t know what a Microchip PolarFire is - you are using tools for the PolarFire which seem to expect other things to be installed to meet it’s dependencies. ---
**Author:** ![stawhite2002](https://avatars.discourse-cdn.com/v4/letter/s/258eb7/32.png) [@stawhite2002](https://forums.freertos.org/u/stawhite2002)\ **Post date:** [May 3, 2022, 8:04am UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/6 "2022-05-03T08:04:02Z")
Exactly. My question, though, is why is there PolarFire FPGA code in a port of FreeRTOS that targets the HiFive platform. Also, as far as I know, there aren’t any PolarFile tools that could manage this code. ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [May 3, 2022, 2:16pm UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/7 "2022-05-03T14:16:35Z")
> [@stawhite2002](#): > > My question, though, is why is there PolarFire FPGA code in a port of FreeRTOS that targets the HiFive platform There isn’t. The only dependency on polarfire is in the tools you are using. ---
**Author:** ![stawhite2002](https://avatars.discourse-cdn.com/v4/letter/s/258eb7/32.png) [@stawhite2002](https://forums.freertos.org/u/stawhite2002)\ **Post date:** [May 4, 2022, 7:17am UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/8 "2022-05-04T07:17:09Z")
The only tools I am using are the CDT builder in SoftConsole and the gnu risc-v toolchain. If they see multiply defined variables or incorrect include paths they are going to fault regardless of whether it’s PolarFire code or something else. Without any switches or #defines, they are going to try and build all the code directories in the project. I don’t see anything in the build to enable bypassing the PolarFire code so that it doesn’t conflict with the FreeRTOS source. ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [May 4, 2022, 4:28pm UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/9 "2022-05-04T16:28:54Z")
I just tried [following the instructions](https://freertos.org/RTOS-RISC-V-FreedomStudio-IAR-HiFive-RevB.html#build_instructions_gcc) to build the project in FreedomStudio and didn’t encounter any problems. I’ve attached the compiler output in case that is useful. [risc-v-build-output.zip](https://forums.freertos.org/uploads/short-url/tVHRCbdyLSsvdHAaYopDuRyUoMV.zip) (5.7 KB) ---
**Author:** ![stawhite2002](https://avatars.discourse-cdn.com/v4/letter/s/258eb7/32.png) [@stawhite2002](https://forums.freertos.org/u/stawhite2002)\ **Post date:** [May 5, 2022, 8:37am UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/10 "2022-05-05T08:37:11Z")
That’s great. The remote computer I’ve been working on has been down for a couple of days, but when it comes back online, I’ll install FreedomStudio and see if it works for me too (and then try and figure out what it’s doing that SoftConsole isn’t). Thanks. ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [May 5, 2022, 1:31pm UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/11 "2022-05-05T13:31:35Z")
I’m not sure why you expect it to build in SoftConsole. ---
**Author:** ![stawhite2002](https://avatars.discourse-cdn.com/v4/letter/s/258eb7/32.png) [@stawhite2002](https://forums.freertos.org/u/stawhite2002)\ **Post date:** [May 7, 2022, 12:26am UTC](https://forums.freertos.org/t/the-sifive-risc-v-port-of-freertos/14960/12 "2022-05-07T00:26:11Z")
Primarily because I just did get it to build in SoftConsole