STM32 xSemaphoreGive Interrupt infinite Loop

Kernel
3

irvind wrote on Thursday, January 06, 2011:

Hi Richard,

I saw point 3 before , but I don’t think I have using any API in ISR. My interrupt handler task as below, please advise.

void USB_LP_CAN_RX0_IRQHandler(void)
{
   
   CAN_Receive(CAN_FIFO0, &RxMessage);
  
   portBASE_TYPE xHighxHigherPriorityTaskWoken = pdFALSE;
   xSemaphoreGiveFromISR( SEM_CAN_INT, &xHighxHigherPriorityTaskWoken);
   portEND_SWITCHING_ISR(xHighxHigherPriorityTaskWoken);
           
}

But I doubt if I really understand well on interrupt priority parts, below are the code I use to enable CAN interrupt.

NVIC_InitStructure.NVIC_IRQChannel=USB_LP_CAN_RX0_IRQChannel;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);

My FreeRTOSConfig.h setting as default.

/* This is the raw value as per the Cortex-M3 NVIC.  Values can be 255
(lowest) to 0 (1?) (highest). */
#define configKERNEL_INTERRUPT_PRIORITY 	255
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	191 /* equivalent to 0xb0, or priority 11. */
/* This is the value being used as per the ST library which permits 16
priority values, 0 to 15.  This must correspond to the
configKERNEL_INTERRUPT_PRIORITY setting.  Here 15 corresponds to the lowest
NVIC value of 255. */
#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY	15

The priority mentioned in point 3 refered to NVIC_IRQChannelPreemptionPriority or create task priority? Which is priority 3 for my task.

Please advise.

Thank you so much for your reply.