STM32 occasionally misses interrupts

Kernel
3

rousea wrote on Monday, September 07, 2015:

Thanks for your prompt response. I added a call to get_BASEPRI() within the fail code above (to copy BASEPRI to a variable) followed by a breakpoint. When this breakpoint was hit I checked various registers to follow your points:

  1. EXT>IMR = 0xFF22, showing that EXTI1 interrupt is enabled. Furthermore EXTI>PR = 0x02, showing that EXTI1 has a pending interrupt

  2. NVIC>PR byte 7 = 0x50, showing that EXTI1 is enabled at priority level 0x50. NVIC>ISER = 0xE000E100, showing that EXTI1 interrupt is enabled. NVIC ISPR = 0xE000E200, showing that EXTI1 interrupt is pending.

  3. BASEPRI = 0

  4. SCB>AIRCR = 0xFA050300, showing that PRIGROUP = 3 (i.e. 16 group levels, no sub-groups)

  5. I may be missing something but I can’t find any way to globally enable/disable interrupts. The nearest I can find is SCB>ICSR, which reads:

    ICSR {…}
    Word 0xc35000
    {…}
    VECTACTIVEL 0x0
    VECTACTIVEH 0x0
    RETTOBASE 0x0
    VECTPENDING_0_3 0x5
    VECTPENDING_4_7 0x3
    ISRPENDING 0x1
    ISRPREEMPT 0x1
    PENDSTCLR 0x0
    PENDSTSET 0x0
    PENDSVCLR 0x0
    PENDSVSET 0x0
    NMIPENDSET 0x0

This confirms that there is a pending ISR but confuses me by saying the vector is 0x35 = dec 53 = USART5. I am not using USART5!

I checked through all the ISR’s and none of them call non interrupt safe API’s.

I am not impressed by the drivers in STM32 Cube. They are not intuitive, are not flexible and don’t allow register contents to be easily analysed. I have therefore created my own drivers, hence the report shown above for SCB>ICSR. It is not therefore practical for me to use ConfigASSERT().

I am currently using FreeRTOS 8.1.2. RTOS task notifications weren’t introduced until V8.2.0. When I resolve this problem I will consider upgrading.

I am therefore no further forward