# Status of floating point register management support on RISC-V port

**URL:** <https://forums.freertos.org/t/status-of-floating-point-register-management-support-on-risc-v-port/17473>\
**Category:** Kernel\
**Created:** [May 23, 2023, 4:41pm UTC](https://forums.freertos.org/t/status-of-floating-point-register-management-support-on-risc-v-port/17473 "2023-05-23T16:41:05Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![ay23](https://avatars.discourse-cdn.com/v4/letter/a/db5fbb/32.png) [@ay23](https://forums.freertos.org/u/ay23)\
**Post date:** [May 23, 2023, 4:41pm UTC](https://forums.freertos.org/t/status-of-floating-point-register-management-support-on-risc-v-port/17473/1 "2023-05-23T16:41:05Z")

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Hello,

I am curious what the status is of FPU/floating point register management on the FreeRTOS port to RISC-V. It looks like at one point it was supported, and then removed? Has it even been added back?

Thanks

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**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\
**Post date:** [May 24, 2023, 5:00am UTC](https://forums.freertos.org/t/status-of-floating-point-register-management-support-on-risc-v-port/17473/2 "2023-05-24T05:00:48Z")

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Floating point support is not yet added.

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**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\
**Post date:** [May 24, 2023, 5:50pm UTC](https://forums.freertos.org/t/status-of-floating-point-register-management-support-on-risc-v-port/17473/3 "2023-05-24T17:50:56Z")

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Some partner supported forks include floating point.

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**Author:** ![ay23](https://avatars.discourse-cdn.com/v4/letter/a/db5fbb/32.png) [@ay23](https://forums.freertos.org/u/ay23)\
**Post date:** [May 24, 2023, 6:38pm UTC](https://forums.freertos.org/t/status-of-floating-point-register-management-support-on-risc-v-port/17473/4 "2023-05-24T18:38:00Z")

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I’m currently running SiFive’s FreeRTOS-Metal port on a custom SOC based on a SiFive E34 core. Although, I’m looking to pivot from the FreeROTS-Metal port, and use the FreeRTOS-kernel RISC-V port instead, due to SiFive’s seeming lack of maintenance & upkeep for their port (even though theirs does support floating point). Do you plan to add support for floating point in the future?

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**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\
**Post date:** [May 24, 2023, 11:16pm UTC](https://forums.freertos.org/t/status-of-floating-point-register-management-support-on-risc-v-port/17473/5 "2023-05-24T23:16:02Z")

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How easy would it be for you create a PR that adds that floating point support into the upstream version?