# SPI1 ISR help

**URL:** <https://forums.freertos.org/t/spi1-isr-help/5050>\
**Category:** Kernel\
**Created:** [March 19, 2009, 1:23pm UTC](https://forums.freertos.org/t/spi1-isr-help/5050 "2009-03-19T13:23:11Z")\
**Posts on this page:** 2\
**Page:** 1

<div class="post-metadata">

**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\
**Post date:** [March 19, 2009, 1:23pm UTC](https://forums.freertos.org/t/spi1-isr-help/5050/1 "2009-03-19T13:23:11Z")

</div>

**[hudson2009](https://sourceforge.net/u/hudson2009/)** wrote on [Thursday, March 19, 2009](https://sourceforge.net/p/freertos/discussion/382005/thread/de205db2/#3900):

Hi,

I am working AT91SAM7X FreeRTOS.  
trying to get the SPI1 working as a slave with interrupt on RDRF.

However the ISR never happen, can any one help?  
Following are initialization code:

//=================================  
//&nbsp; ARM7 SPI1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MSP430 SPIA  
// -----------&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ----------  
//&nbsp;&nbsp;&nbsp;&nbsp; PA21&nbsp; |\<- NCPS0 -&nbsp; | P3.7  
//&nbsp;&nbsp;&nbsp;&nbsp; PA22&nbsp; |\<- SCLK -&nbsp;&nbsp; | P3.0  
//&nbsp;&nbsp;&nbsp;&nbsp; PA23&nbsp; |\< - MOSI -&nbsp; | P3.4  
//&nbsp;&nbsp;&nbsp;&nbsp; pa24&nbsp; | - MISO -\>&nbsp; | P3.5  
// -----------&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ----------  
//=================================  
void vSPI1\_Init(void)  
{

&nbsp; portENTER\_CRITICAL();  
&nbsp; {  
&nbsp;&nbsp;&nbsp; // Config SPI1 PIO -  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_PIOA -\>PIO\_PDR = (AT91C\_PA21\_NPCS10| AT91C\_PA24\_MISO1 | AT91C\_PA23\_MOSI1 | AT91C\_PA22\_SPCK1);// Set in Periph mode  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_PIOA -\>PIO\_BSR = (AT91C\_PA21\_NPCS10| AT91C\_PA24\_MISO1 | AT91C\_PA23\_MOSI1 | AT91C\_PA22\_SPCK1);&nbsp;&nbsp;&nbsp;  
&nbsp;&nbsp;&nbsp;  
&nbsp;&nbsp;&nbsp; // Config PMC  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_PMC-\>PMC\_PCER = 1 \<\< AT91C\_ID\_SPI1;

&nbsp;&nbsp;&nbsp; //SPI software reset  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_SPI1-\>SPI\_CR = AT91C\_SPI\_SWRST;

&nbsp;&nbsp; // cfg MR 9slave mode)  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_SPI1-\>SPI\_MR = AT91C\_SPI\_MODFDIS;

&nbsp;&nbsp; // cfg CSR  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_SPI1-\>SPI\_CSR[0] = (0 + 0 + AT91C\_SPI\_BITS\_8);

&nbsp;&nbsp;&nbsp; // Configure SPI interrupt  
&nbsp;&nbsp;&nbsp; // AT91F\_AIC\_ConfigureIt  
&nbsp;&nbsp;&nbsp; //----------------------------------------------------------------------------------------------------&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_AIC-\>AIC\_IDCR = 0x01\<\< AT91C\_ID\_SPI1;  
&nbsp;&nbsp;&nbsp; // Save the interrupt handler routine pointer and the interrupt priority  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_AIC-\>AIC\_SVR[AT91C\_ID\_SPI1] = (unsigned int)vSPI\_ISR\_Wrapper;  
&nbsp;&nbsp;&nbsp; // Store the Source Mode Register  
&nbsp;&nbsp;&nbsp; //AT91C\_BASE\_AIC-\> AIC\_SMR[AT91C\_ID\_SPI1]= AT91C\_AIC\_PRIOR\_HIGHEST | AT91C\_AIC\_SRCTYPE\_INT\_POSITIVE\_EDGE ;  
&nbsp;&nbsp;&nbsp; // Clear the interrupt on the interrupt controller  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_AIC-\>AIC\_ICCR = 0x01\<\< AT91C\_ID\_SPI1;  
&nbsp;&nbsp;&nbsp; //----------------------------------------------------------------------------------------------------&nbsp;&nbsp;  
&nbsp;&nbsp;&nbsp; //AT91F\_AIC\_EnableIt  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_AIC-\>AIC\_IECR = 0x1 \<\< AT91C\_ID\_SPI1;

&nbsp;&nbsp;&nbsp; // Enable interrupt aacordingly  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_SPI1 -\> SPI\_IDR =&nbsp; (AT91C\_SPI\_RDRF + AT91C\_SPI\_TDRE + AT91C\_SPI\_MODF + AT91C\_SPI\_OVRES+  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AT91C\_SPI\_NSSR + AT91C\_SPI\_TXEMPTY + AT91C\_SPI\_SPIENS);  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_SPI1 -\> SPI\_IER =&nbsp; AT91C\_SPI\_RDRF;

&nbsp;&nbsp;&nbsp; // Disable the PDC transfer&nbsp;&nbsp;&nbsp;  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_SPI1-\>SPI\_PTCR = AT91C\_PDC\_RXTDIS | AT91C\_PDC\_TXTDIS;

&nbsp;&nbsp; // SPI is enable  
&nbsp;&nbsp;&nbsp; AT91C\_BASE\_SPI1-\>SPI\_CR = AT91C\_SPI\_SPIEN;

&nbsp; }  
&nbsp; portEXIT\_CRITICAL();  
}

void vSPI1\_ISR\_Wrapper( void )\_\_attribute\_\_ ((naked));  
void vSPI1\_ISR\_Handler( void );

void vSPI1\_ISR\_Wrapper( void )  
{  
&nbsp;&nbsp;&nbsp; portSAVE\_CONTEXT();  
&nbsp;&nbsp;&nbsp; vSPI\_ISR\_Handler();  
&nbsp;&nbsp;&nbsp; portRESTORE\_CONTEXT();  
}

/\*-----------------------------------------------------------\*/  
void vSPI1\_ISR\_Handler( void )  
{  
&nbsp;&nbsp;&nbsp;&nbsp; unsigned long spi\_Status;&nbsp;&nbsp;&nbsp;  
&nbsp;&nbsp;&nbsp;&nbsp; signed portCHAR RxChar;  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AT91PS\_SPI&nbsp;&nbsp;&nbsp;&nbsp; pSPI = AT91C\_BASE\_SPI1;  
&nbsp;&nbsp;&nbsp;  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; spi\_Status = (pSPI -\> SPI\_SR);  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;  
&nbsp;&nbsp;&nbsp; // A data has been recieved and transmitted to the RBR.  
&nbsp;&nbsp;&nbsp; if (spi\_Status & AT91C\_SPI\_RDRF)&nbsp;&nbsp;&nbsp;  
&nbsp;&nbsp;&nbsp; {  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; spi\_Rdrf\_Flag = 1;  
&nbsp;&nbsp;&nbsp; }  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /\* End the interrupt in the AIC. \*/  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AT91C\_BASE\_AIC-\>AIC\_EOICR = 0;  
}  
/\*-----------------------------------------------------------\*/

---

<div class="post-metadata">

**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\
**Post date:** [March 19, 2009, 3:56pm UTC](https://forums.freertos.org/t/spi1-isr-help/5050/2 "2009-03-19T15:56:03Z")

</div>

**[hudson2009](https://sourceforge.net/u/hudson2009/)** wrote on [Thursday, March 19, 2009](https://sourceforge.net/p/freertos/discussion/382005/thread/de205db2/#3900/7a03):

found the problem.

MASTER not driving the CS line LOW.

😛