Simple TCP Echo server - does not respond to ping

andrei799 wrote on Tuesday, October 24, 2017:

CPU’s operating frequency is 300 MHz.

heinbali01 wrote on Thursday, October 26, 2017:

In that case it is indeed possible that 4 TX buffers are occupied at the same time.
I did write a zero-copy driver ( at the transmission site ), but I’m waiting for a SAME70 board to test it.

heinbali01 wrote on Monday, November 20, 2017:

Hi Andrei, do you have the driver already working?

I finally have a SAME70 Xplained board here for testing.

What I found is that the driver must set dummy descriptors in the priority queues, even if you do not use them:

+COMPILER_ALIGNED(8)
+    static gmac_tx_descriptor_t gs_tx_desc_null;

     /* Set transmit buffer queue */
     gmac_set_tx_queue(p_hw, (uint32_t) p_td);
+    gmac_set_tx_priority_queue(p_hw, (uint32_t)&gs_tx_desc_null, GMAC_QUE_1);
+    gmac_set_tx_priority_queue(p_hw, (uint32_t)&gs_tx_desc_null, GMAC_QUE_2);

Otherwise the DMA transmission unit finds an invalid TX descriptor at address 0x00.

andrei799 wrote on Tuesday, November 21, 2017:

Hello Hein,

Yes, the driver is working since you gave me the solution - set Rx Buffer Offset to 2. Thanks again!

Dummy descriptors in the priority queues were set (the difference is that first I am setting GMAC_QUE_2 and then GMAC_QUE_1 but this should not be an issue) .

heinbali01 wrote on Tuesday, November 21, 2017:

Andrei, I will try to bring out a unified version of the +TCP driver, which will work for bot SAM4E, and SAME70.
The transmission will be zero-copy. The reception can not be made zero-copy for +FAT, as it uses small fixed-size RX buffers.
Right now I’m fighting with the SAME70 TC (Timer Counter), which is only 16-bits. I want to cascade two of them in order to get a 32-bit performance timer.

andrei799 wrote on Monday, April 23, 2018:

Hello Hein,
Did you implemented the unified version? I am just curious.
Please be aware that are some differences between ATSAME70Q21 (Rev. A mounted on Xplained board) and new ATSAME70Q21B (Rev. B). That last revision (B) does fix some silicon bugs which affects GMAC queues therefore the code is not a drop-in replacement and must be updated.

Differences between the 2 revisions can be found here:
http://ww1.microchip.com/downloads/en/DeviceDoc/80000767A.PDF

Hope it helps.

Best Regards,
Andrei