# Running FreeRTOS with IAR v5.10

**URL:** <https://forums.freertos.org/t/running-freertos-with-iar-v5-10/3894>\
**Category:** Kernel\
**Created:** [August 3, 2007, 7:29pm UTC](https://forums.freertos.org/t/running-freertos-with-iar-v5-10/3894 "2007-08-03T19:29:19Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\
**Post date:** [August 3, 2007, 7:29pm UTC](https://forums.freertos.org/t/running-freertos-with-iar-v5-10/3894/1 "2007-08-03T19:29:19Z")

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**[syu49](https://sourceforge.net/u/syu49/)** wrote on [Friday, August 03, 2007](https://sourceforge.net/p/freertos/discussion/382005/thread/add436f5/#9fc1):

I have currently upgrade my IAR from v4.40 to v5.10.&nbsp; I was able to run the Web sever demo with STR912x before with v4.40.&nbsp; After the upgrade, I was able to compile the code, but not being able to make it run.&nbsp; I have modified the linker file and several other assembly files, but still have no luck.&nbsp; Just wonder whether anyone has able to make it run with v5.10.

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**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\
**Post date:** [August 3, 2007, 8:53pm UTC](https://forums.freertos.org/t/running-freertos-with-iar-v5-10/3894/2 "2007-08-03T20:53:36Z")

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**[rtel](https://sourceforge.net/u/rtel/)** wrote on [Friday, August 03, 2007](https://sourceforge.net/p/freertos/discussion/382005/thread/add436f5/#9fc1/6622):

I have a copy of V5 but have not yet installed it.&nbsp; From the marketing info it seems that there are several manual updates that are required to the system code, although I cannot remember what they are.

It sounds like you have got quite a way into this.&nbsp; When you modified the asm files, did you remember to ensure the kernel is started from Supervisor mode?&nbsp; Also that the IRQ and Supervisor stacks are setup?

Regards.

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**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\
**Post date:** [August 3, 2007, 10:38pm UTC](https://forums.freertos.org/t/running-freertos-with-iar-v5-10/3894/3 "2007-08-03T22:38:26Z")

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**[syu49](https://sourceforge.net/u/syu49/)** wrote on [Friday, August 03, 2007](https://sourceforge.net/p/freertos/discussion/382005/thread/add436f5/#9fc1/7b89):

Here is what I have in the 91x\_init.s file for setting up the stack

; Enter each mode in turn and set up the stack pointer

&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MSR&nbsp;&nbsp;&nbsp;&nbsp; CPSR\_c, #Mode\_FIQ|I\_Bit|F\_Bit&nbsp;&nbsp;&nbsp; ; No interrupts  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDR&nbsp;&nbsp;&nbsp;&nbsp; SP, =SFE(FIQ\_STACK)

&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MSR&nbsp;&nbsp;&nbsp;&nbsp; CPSR\_c, #Mode\_IRQ|I\_Bit|F\_Bit&nbsp;&nbsp;&nbsp; ; No interrupts  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDR&nbsp;&nbsp;&nbsp;&nbsp; SP, = SFE(IRQ\_STACK)

&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MSR&nbsp;&nbsp;&nbsp;&nbsp; CPSR\_c, #Mode\_ABT|I\_Bit|F\_Bit&nbsp;&nbsp;&nbsp; ; No interrupts  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDR&nbsp;&nbsp;&nbsp;&nbsp; SP, = SFE(ABT\_STACK)  
&nbsp;&nbsp;&nbsp;  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MSR&nbsp;&nbsp;&nbsp;&nbsp; CPSR\_c, #Mode\_UND|I\_Bit|F\_Bit&nbsp;&nbsp;&nbsp; ; No interrupts  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDR&nbsp;&nbsp;&nbsp;&nbsp; SP, = SFE(UND\_STACK)

&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MSR&nbsp;&nbsp;&nbsp;&nbsp; CPSR\_c, #Mode\_SVC|I\_Bit|F\_Bit&nbsp;&nbsp;&nbsp; ; No interrupts  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDR&nbsp;&nbsp;&nbsp;&nbsp; SP, = SFE(SVC\_STACK)

&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MSR&nbsp;&nbsp;&nbsp;&nbsp; CPSR\_c, #Mode\_SYS|I\_Bit|F\_Bit&nbsp;&nbsp;&nbsp; ; No interrupts  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDR&nbsp;&nbsp;&nbsp;&nbsp; SP, = SFE(USR\_STACK)

; — Set bits 17-18(DTCM/ITCM order bits)of the Core Configuration Control  
;&nbsp;&nbsp;&nbsp;&nbsp; Register  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MOV&nbsp;&nbsp;&nbsp;&nbsp; r0, #0x60000  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MCR&nbsp;&nbsp;&nbsp;&nbsp; p15,0x1,r0,c15,c1,0

; — Now change to supervise mode and set up User mode stack,  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MSR&nbsp;&nbsp;&nbsp;&nbsp; CPSR\_c, #Mode\_SVC|I\_Bit|F\_Bit&nbsp;&nbsp; ; No interrupts  
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDR&nbsp;&nbsp;&nbsp;&nbsp; SP, = SFE(CSTACK)

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<div class="post-metadata">

**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\
**Post date:** [August 8, 2007, 2:10pm UTC](https://forums.freertos.org/t/running-freertos-with-iar-v5-10/3894/4 "2007-08-08T14:10:05Z")

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**[xaw](https://sourceforge.net/u/xaw/)** wrote on [Wednesday, August 08, 2007](https://sourceforge.net/p/freertos/discussion/382005/thread/add436f5/#9fc1/1e6a):

Hi,

First I must tell you that I use another board, but it doesnt really matter since I have the same problem than you.  
I was running the uIP web server on my board using IAR 4.X and it works fine. Now I am using 5.10 and it doesnt go very well.

I had some data abort exception and this is where I went on this forum.  
I saw your following post  
; — Now change to supervise mode and set up User mode stack,  
MSR CPSR\_c, #Mode\_SVC|I\_Bit|F\_Bit ; No interrupts  
LDR SP, = SFE(CSTACK)

And that helps me a bit.  
I was running in system mode instead of supervisor mode.  
Now I don’t have the same problem.  
I have stripped out the web server code and I tried to run FreeRTOS with only one task running ( a blinking led task).  
When the task enter in vTaskDelayUntil, it never gets out of it.  
The idle task seems to be the only one running.

Regards