# RH850 U2A8 multicore porting (R7F702301A) **URL:** \ **Category:** Kernel\ **Tags:** tutorial\ **Created:** [July 4, 2024, 12:01pm UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884 "2024-07-04T12:01:43Z")\ **Posts on this page:** 15\ **Page:** 1
**Author:** ![Eshwar](https://avatars.discourse-cdn.com/v4/letter/e/d2c977/32.png) [@Eshwar](https://forums.freertos.org/u/Eshwar)\ **Post date:** [July 4, 2024, 12:01pm UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/1 "2024-07-04T12:01:43Z")
Hello, I have a working reference for FreeRTOS v10.4.1 ported to RH850 single core (R7F701645) which uses the Renesas CCRH compiler From my desk research, the multi-core support is added from v11 so I will be attempting to upgrade the existing RTOS version of mine on single core first I can sum up the porting as an implementation of 6 functions (in port.c assembly syntax) and making changes to boot up code for the single-core MCU that I used 1. trap\_set 2. portSAVE\_CONTEXT 3. portRESTORE\_CONTEXT 4. vPortYield 5. vPortStart 6. vPortSetupTimerInterrupt Similarly, I am looking for a reference for the RH850 port that has the changes to be done to enable multi-core support - Are there any additional port assy functions to be implemented for this? - Is there any reference port available for reference that closely matches RH850 U2A8 R7F702301A Kindly suggest ---
**Author:** ![karahulx](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/karahulx/32/4893_2.png) [@karahulx](https://forums.freertos.org/u/karahulx)\ **Post date:** [July 4, 2024, 6:50pm UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/2 "2024-07-04T18:50:45Z")
Hi @Eshwar Welcome to the FreeRTOS Community Forums ! [Here](https://forums.freertos.org/t/freertos-ported-to-rh850/11279) is an example of a basic port of FreeRTOS to RH850 . This is the discussion [thread](https://forums.freertos.org/t/freertos-ported-to-rh850/11279) for the porting mechanism. Let us know if this helps. Thanks. ---
**Author:** ![Eshwar](https://avatars.discourse-cdn.com/v4/letter/e/d2c977/32.png) [@Eshwar](https://forums.freertos.org/u/Eshwar)\ **Post date:** [July 5, 2024, 6:08am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/3 "2024-07-05T06:08:26Z")
Hi, Thanks for the reply. I have achieved porting on RH850 single-core CPU Kindly suggest the necessary steps (or porting) for enabling multi-core support Is there any reference port? ---
**Author:** ![karahulx](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/karahulx/32/4893_2.png) [@karahulx](https://forums.freertos.org/u/karahulx)\ **Post date:** [July 5, 2024, 7:25am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/4 "2024-07-05T07:25:00Z")
Hi, Thanks for reporting back. This discussion [thread](https://forums.freertos.org/t/smp-porting-checklist-a53-4-as-reference/14499) provides a good starting point for porting your single-core to multi-core support. ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [July 8, 2024, 4:41am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/5 "2024-07-08T04:41:59Z")
> [@Eshwar](#): > > Is there any reference port? Here are some SMP ports - - [FreeRTOS-Kernel/portable/ThirdParty/xClang/XCOREAI at main · FreeRTOS/FreeRTOS-Kernel · GitHub](https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/ThirdParty/xClang/XCOREAI) - [FreeRTOS-Kernel/portable/ThirdParty/GCC/RP2040 at main · FreeRTOS/FreeRTOS-Kernel · GitHub](https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/ThirdParty/GCC/RP2040) - [FreeRTOS-Kernel-Partner-Supported-Ports/TI/CORTEX\_A53\_64-BIT\_TI\_AM64\_SMP at main · FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports · GitHub](https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports/tree/main/TI/CORTEX_A53_64-BIT_TI_AM64_SMP) ---
**Author:** ![tringuyen](https://avatars.discourse-cdn.com/v4/letter/t/a9a28c/32.png) [@tringuyen](https://forums.freertos.org/u/tringuyen)\ **Post date:** [October 29, 2024, 2:25pm UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/6 "2024-10-29T14:25:21Z")
Hi Eshwar, I have a U2A8 CS+/CCRH project sample that demonstrate multiple instances of FreeRTOS running on different cores (Asymmetric multiprocessing). If you think this could be helpful, please provide me with your contact details, I am happy to share it with you. Best Regards, Tri Nguyen ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [November 4, 2024, 5:12am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/7 "2024-11-04T05:12:28Z")
You can also contribute your sample here - [GitHub - FreeRTOS/FreeRTOS-Community-Supported-Demos](https://github.com/FreeRTOS/FreeRTOS-Community-Supported-Demos). ---
**Author:** ![tringuyen](https://avatars.discourse-cdn.com/v4/letter/t/a9a28c/32.png) [@tringuyen](https://forums.freertos.org/u/tringuyen)\ **Post date:** [November 4, 2024, 7:31am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/8 "2024-11-04T07:31:27Z")
Thanks for the suggestions. The AMP project on U2A8 is currently using an older version of FreeRTOS. I will create a PR after testing with the latest FreeRTOS version, following the provided demo template. Meanwhile, I am working on an SMP port and have encountered an issue. Question: How do secondary cores manage their task scheduling after the primary core triggers their first task via an IPI? Issue: During SMP porting, Core 1 is getting stuck in an infinite sequence loop involving trap interrupts. The sequence call of core 1 as the below: ```auto IPI ISR -> _vPortStartFirstTask -> _vPortYield -> (loop: _vTRAP0_Handler -> _vTaskSwitchContext -> _vTRAP0_Handler_Exit -> Core 1 first task -> vTaskDelay -> xTaskResumeAll -> _vPortYield) ``` This results in Core 1 continuously calling the same task regardless of its cycle and almost occupies the spinlock on Core 0. I am testing with simple demo where each core is just running a cyclic task, and the porting code is not significantly different from the porting code provided, [FreeRTOS-Kernel/portable/CCRH/F1Kx at main · FreeRTOS/FreeRTOS-Kernel · GitHub](https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/CCRH/F1Kx). Any insights or guidance would be greatly appreciated. Thank you in advance! ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [November 5, 2024, 6:54am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/9 "2024-11-05T06:54:30Z")
> [@tringuyen](#): > > This results in Core 1 continuously calling the same task regardless of its cycle and almost occupies the spinlock on Core 0. Why does Core 1 not pick the idle task when the currently running task is blocked (because it called vTaskDelay)? ---
**Author:** ![tringuyen](https://avatars.discourse-cdn.com/v4/letter/t/a9a28c/32.png) [@tringuyen](https://forums.freertos.org/u/tringuyen)\ **Post date:** [November 6, 2024, 12:00pm UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/10 "2024-11-06T12:00:18Z")
Thank you for your hint. The issue is that the ‘uxCoreAffinityMask’ for the idle task on core 1 is set to ‘1’. Where is this 'uxCoreAffinityMask` assigned to ‘2’ for core 1? I have tried to modify it manually in prvCreateIdleTasks() ![image](https://d2v6vdsk2p900z.cloudfront.net/original/2X/c/c5c3b39c873ce20a10ac9c6fc7bbe8b95ea710cb.png), but core 0 raised an exception while core 1 only executes its idle task after a while. There may be an issue with both cores accessing the same pxReadyTasksLists, which causes it to break (core 0 raises an exception at the line: if( listCURRENT\_LIST\_LENGTH( &( pxReadyTasksLists[tskIDLE\_PRIORITY] ) ) \> ( UBaseType\_t ) configNUMBER\_OF\_CORES in prvIdleTask) ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [November 7, 2024, 6:32am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/11 "2024-11-07T06:32:49Z")
> [@tringuyen](#): > > The issue is that the ‘uxCoreAffinityMask’ for the idle task on core 1 is set to ‘1’. > Where is this 'uxCoreAffinityMask` assigned to ‘2’ for core 1? This seems correct as core affinity is a bitmask. Why do you think it is an issue? > [@tringuyen](#): > > There may be an issue with both cores accessing the same pxReadyTasksLists, which causes it to break This should not happen assuming that you have implemented all the SMP related lock macros correctly. Take a look here for example - [FreeRTOS-Kernel/portable/ThirdParty/GCC/RP2040/include/portmacro.h at main · FreeRTOS/FreeRTOS-Kernel · GitHub](https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/portable/ThirdParty/GCC/RP2040/include/portmacro.h#L262-L265). ---
**Author:** ![tringuyen](https://avatars.discourse-cdn.com/v4/letter/t/a9a28c/32.png) [@tringuyen](https://forums.freertos.org/u/tringuyen)\ **Post date:** [November 7, 2024, 10:43am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/12 "2024-11-07T10:43:00Z")
Thank you for your response. The core affinity is not an issue; the problem is due to an incorrect implementation of the inter-processor interrupt, which inadvertently triggers the ISR on both cores. For reference, there’s a branch porting FreeRTOS to RH850/U2Ax and U2Bx here: [FreeRTOS-Kernel-Partner-Supported-Ports/CCRH/U2x at u2x\_port](https://github.com/renesas/FreeRTOS-Kernel-Partner-Supported-Ports/tree/u2x_port/CCRH/U2x). Once again, I really appreciate your valuable feedback. ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [November 7, 2024, 11:05am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/13 "2024-11-07T11:05:31Z")
> [@tringuyen](#): > > the problem is due to an incorrect implementation of the inter-processor interrupt, which inadvertently triggers the ISR on both cores. Ah, I see - Good find! I think the solution should be to fix this? ---
**Author:** ![tringuyen](https://avatars.discourse-cdn.com/v4/letter/t/a9a28c/32.png) [@tringuyen](https://forums.freertos.org/u/tringuyen)\ **Post date:** [November 8, 2024, 3:48am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/14 "2024-11-08T03:48:24Z")
Yes, the issue was fixed by making a correction in IPI initialization. ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [November 10, 2024, 8:31am UTC](https://forums.freertos.org/t/rh850-u2a8-multicore-porting-r7f702301a/20884/15 "2024-11-10T08:31:53Z")
Thank you for sharing!