Quetions about the task scheduler

[aggarg (Gaurav Aggarwal)]

@Yueming

A higher priority IRQ occurs, tick IRQ is switched out. The higher priority IRQ adds a ready task into the ready list and sets uxTopReadyPriority to this task’s priority, let’s assume it is 6.

Reading above, I assume that you are talking about ports which support interrupt nesting. Taking an example of Cortex-M4 - before vTaskSwitchContext is called, all the interrupts which can call FreeRTOS APIs (and as a result can alter FreeRTOS lists) are masked: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/portable/GCC/ARM_CM4F/port.c#L463. So the scenario you mentioned is not possible. You can look at this response to understand interrupt priorities in Cortex-M: Understanding priority levels of ISR and FreeRTOS APIs - #16 by aggarg

Again, as Richard said, if you think there is a bug in a specific port, let us know the port.

Thanks.