That sounds like a good idea. Would you like to raise a PR for that?
Yes Iâd be happy to. Detect more startup config errors on Cortex M by jefftenney ¡ Pull Request #832 ¡ FreeRTOS/FreeRTOS-Kernel ¡ GitHub.
1 Like
Great work Jeff 
Do you think the change is useful for ARM_CM3 port, too ?
Yes, I plan to replicate to all the ARMv7-M and ARMv8-M targets in the same PR. (The PR is currently a âdraftâ for this reason.)
I hope to replicate to ARMv6-M too, but I will need to review the ARMv6-M reference manual regarding VTOR and the address of the vector table when VTOR is not implemented. For example, if VTOR is not implemented but is specified as RAZ, and if the vector table in that case is required to reside at 0x00000000, then ARMv7-M code would also work on ARMv6-M as is. If not, it may be difficult to port to ARMv6-M. Advice welcome!
STBuggyCodeGen.zip (1.3 MB)
Here is the generated code by CubeMX6.2.1 .
But, I have played around with a version above and below 6.2.0 and 6.2.2 and has the same genearation. So I think is corrupted for all STM32H7 series (so far) I think
From STM GIT repo, I downloaded the system file for STM32H7 file and replacing this one in the project resolves the issue.
system_stm32h7xx.c (11.3 KB)
I havenât had the time to look into the diff yet. Probaby this weekend I can get a couple of mins to check this.
Using STM32H725IGK6 and STM32H755IGK6 andgenerated code from STMCube 1.31.1 IDE integrated with CubeMX 6.2.1.
Generated the code by creating and .ioc file. Enabled Freertos by enabling it from Middleware and Software Packs. Added a tasks using Tasks and Queue. Thatâs it.
I built the code in the zip you shared.
Looking at the map file, I can see that both SVC and PendSV handler are coming from FreeRTOS:
.text.PendSV_Handler
0x0000000008003f20 0x68 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
0x0000000008003f20 PendSV_Handler
.text.SVC_Handler
0x0000000008003cd0 0x28 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o
0x0000000008003cd0 SVC_Handler
Examining the first couple of bytes in the ELF shows the correct addresses in the binary as well:
arm-none-eabi-objdump.exe -s -j .isr_vector .\BuggyCodeGen.elf
.\BuggyCodeGen.elf: file format elf32-littlearm
Contents of section .isr_vector:
8000000 00000524 19060008 e1040008 e7040008 ...$............
8000010 ed040008 f3040008 f9040008 00000000 ................
8000020 00000000 00000000 00000000 d13c0008 .............<..
8000030 ff040008 00000000 213f0008 0d050008 ........!?......
How are you programming the binary to the board?
Comparing the system_stm32h7xx.c from the project and the one from STM git repo (attached seperately):
system_stm32h7xx.c from the project:
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */
#else
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
*/
FMC_Bank1_R->BTCR[0] = 0x000030D2;
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */
#endif /*DUAL_CORE && CORE_CM4*/
SCB->VTOR is set only when USER_VECT_TAB_ADDRESS is defined and the definition of USER_VECT_TAB_ADDRESS is commented out and the description indicates USER_VECT_TAB_ADDRESS must be defined to relocate vector table to either FLASH BANK1 (in this case) or XI SRAM. If not, then VTOR is not set and would have reset value (0x0). I believe this is the case and causing the fault observed.
The definitioin of USER_VECT_TAB_ADDRESS:
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
#if defined(DUAL_CORE) && defined(CORE_CM4)
/*!< Uncomment the following line if you need to relocate your vector Table
in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#endif /* VECT_TAB_SRAM */
#else
/*!< Uncomment the following line if you need to relocate your vector Table
in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x400. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
#endif /* VECT_TAB_SRAM */
#endif /* DUAL_CORE && CORE_CM4 */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
system_stm32h7xx.c from STM git repo (attached seperately)
With this it works as expected because of the following.
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
To summarise, defining USER_VECT_TAB_ADDRESS in the project should also fix the issue observed. But an alternate solution to set the VTOR is already in STM git repo.
@jefftenney The changes you proposed would have certainly caught this issue, if already implemented.
I have a Nucleo board with STM32H743ZI and the code generated with STM32CubeIDE it works without defining USER_VECT_TAB_ADDRESS.
The following is from the Boot Configuration section of the Reference Manual:
@rlobo - Are you using a custom board? If yes, what is value of BOOT pin? Can you check the option bytes BOOT_ADD0 and BOOT_ADD1 ? I think you are booting into the system boolloader because BOOT pin is high. Can you try pulling BOOT pin low?
@aggarg No I havenât used a custom board to test this issue. I used the Discovery Kit for STM32H735IGKX.
Assuming that it is this kit, what is the location of SW1 switch:
Freaks! That was the cause all the while so far. Thanks @aggarg
Glad that it worked for you!