# PIC32MZ EF with FPU AddressErrorException in isr **URL:** \ **Category:** Kernel\ **Created:** [March 28, 2017, 1:27pm UTC](https://forums.freertos.org/t/pic32mz-ef-with-fpu-addresserrorexception-in-isr/6505 "2017-03-28T13:27:03Z")\ **Posts on this page:** 3\ **Page:** 1
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [March 28, 2017, 1:27pm UTC](https://forums.freertos.org/t/pic32mz-ef-with-fpu-addresserrorexception-in-isr/6505/1 "2017-03-28T13:27:03Z")
**[poweruli](https://sourceforge.net/u/poweruli/)** wrote on [Tuesday, March 28, 2017](https://sourceforge.net/p/freertos/discussion/382005/thread/6261c488/#0170): Hello, the xISRStack needs to be 8 Byte aligned for PIC32 MZ EF with FPU and it is not 8 byte aligned. Error occurs only when the hardware floating point option is released in the compiler. The MIPS® Architecture For Programmers manual is written: Restrictions: An AddressErrorException occurs if EffectiveAddress2…0 ≠ 0 (not doubleword-aligned). Original FreeRTOS V9.00 Source: File port.c Line 192: StackType\_t xISRStack[configISR\_STACK\_SIZE] = { 0 }; const StackType\_t \* const xISRStackTop = &( xISRStack[configISR\_STACK\_SIZE - 7] ); My suggestion to improve is : StackType\_t **attribute** ((aligned (8))) xISRStack[(configISR\_STACK\_SIZE & 0xFFFFFFFE)] = { 0 } const StackType\_t \* const xISRStackTop = &( xISRStack[(configISR\_STACK\_SIZE & 0xFFFFFFFE) - 8] ); Best regards, Uli ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [March 28, 2017, 2:21pm UTC](https://forums.freertos.org/t/pic32mz-ef-with-fpu-addresserrorexception-in-isr/6505/2 "2017-03-28T14:21:57Z")
**[rtel](https://sourceforge.net/u/rtel/)** wrote on [Tuesday, March 28, 2017](https://sourceforge.net/p/freertos/discussion/382005/thread/6261c488/#0170/4ab8): Hi Uli - thanks for taking the time. This problem was already noted, although the fix in not publicly available yet. The relevant part of the updated code is below. I would be grateful if you could try it and confirm it fixes your issue. The original code is commented out, and the replacement code following immediately after: ``` /* The stack used by interrupt service routines that cause a context switch. 8 byte alignment is required to allow double word floating point stack pushes generated by the compiler. */ //StackType_t xISRStack[configISR_STACK_SIZE] = { 0 }; StackType_t xISRStack[configISR_STACK_SIZE] __attribute__ ( ( aligned( 8 ) ) ) = { 0 }; /* The top of stack value ensures there is enough space to store 6 registers on the callers stack, as some functions seem to want to do this. */ //const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] ); const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 8 ] ); ``` ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [March 29, 2017, 11:19am UTC](https://forums.freertos.org/t/pic32mz-ef-with-fpu-addresserrorexception-in-isr/6505/3 "2017-03-29T11:19:41Z")
**[poweruli](https://sourceforge.net/u/poweruli/)** wrote on [Wednesday, March 29, 2017](https://sourceforge.net/p/freertos/discussion/382005/thread/6261c488/#0170/4ab8/21c9): Hi Real Time Engineers, this code fixed the issue and it’s semilar to my suggestion, excecpt the optional mask (configISR\_STACK\_SIZE & 0xFFFFFFFE). I have made this to ensure that any defenition of configISR\_STACK\_SIZE size will work. Default is 400 and it’s ok, but odd sizes may result in 4 Byte aligned top of stack. An additional information text in the FreeRTOSConfig.h would also be useful. Thank you also for your quick response!