# PIC32MZ Assert/exception in vListInsertEnd() **URL:** \ **Category:** Kernel\ **Created:** [November 4, 2014, 4:34pm UTC](https://forums.freertos.org/t/pic32mz-assert-exception-in-vlistinsertend/1942 "2014-11-04T16:34:14Z")\ **Posts on this page:** 6\ **Page:** 1
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [November 4, 2014, 4:34pm UTC](https://forums.freertos.org/t/pic32mz-assert-exception-in-vlistinsertend/1942/1 "2014-11-04T16:34:14Z")
**[jmmag](https://sourceforge.net/u/jmmag/)** wrote on [Tuesday, November 04, 2014](https://sourceforge.net/p/freertos/discussion/382005/thread/5874244d/#7975): As a preface, I had typed up a lengthy post describing my methods for diagnosing this problem, but lost it without warning when the page navigated to the ‘CodeHilite’ documentation. So I apologize in advance if this initial post does not seem as detailed (or marked-up) as what it would have been. Anyway, I have been encountering issues when sending messages from a DMA ISR to a task queue via xQueueSendFromISR(). The address error exception occurs at this line: pxIndex-\>pxPrevious-\>pxNext = pxNewListItem; and when debugging I see that the stack is indeed overflowing, but have tried a number of things to address the issue (increasing stack, configMAX\_SYSCALL\_INTERRUPT\_PRIORITY, etc.) without much success. Any help would be appreciated. Thanks, Jon ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [November 4, 2014, 7:24pm UTC](https://forums.freertos.org/t/pic32mz-assert-exception-in-vlistinsertend/1942/2 "2014-11-04T19:24:34Z")
**[edwards3](https://sourceforge.net/u/edwards3/)** wrote on [Tuesday, November 04, 2014](https://sourceforge.net/p/freertos/discussion/382005/thread/5874244d/#4f02): The PIC32 port uses configISR\_STACK\_SIZE in FreeRTOSConfig.h to size the stack used by interrupts. Have you tried increasing that? ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [November 4, 2014, 8:35pm UTC](https://forums.freertos.org/t/pic32mz-assert-exception-in-vlistinsertend/1942/3 "2014-11-04T20:35:33Z")
**[jmmag](https://sourceforge.net/u/jmmag/)** wrote on [Tuesday, November 04, 2014](https://sourceforge.net/p/freertos/discussion/382005/thread/5874244d/#a240): Yes, I stopped at 8k; furthermore all of my ISR variables are either global or static and the queue element is only 4 ints in size. I have [found](https://sourceforge.net/p/freertos/discussion/382005/thread/a55c744b/) a few [different threads](https://sourceforge.net/p/freertos/discussion/382005/thread/f1151277/) that deal with [similar](https://sourceforge.net/p/freertos/discussion/382005/thread/20cf7379/) issues, but none seem to match mine exactly. Although, [this post](https://sourceforge.net/p/freertos/discussion/382005/thread/9da2e384/#5226) seems to describe my situation of the exponential stack usage, but the ISR flags aren’t reset until after xQueueSendFromISR() finishes. So there should be no chance for recursion, at least above the hood. Jon ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [November 4, 2014, 8:41pm UTC](https://forums.freertos.org/t/pic32mz-assert-exception-in-vlistinsertend/1942/4 "2014-11-04T20:41:26Z")
**[rtel](https://sourceforge.net/u/rtel/)** wrote on [Tuesday, November 04, 2014](https://sourceforge.net/p/freertos/discussion/382005/thread/5874244d/#a240/7161): There are two ways of defining interrupts on the PIC32. One uses the compiler syntax to get the compiler to generate the interrupt entry code, the other uses an assembly file wrapper to switch stacks on interrupt entry in order to save a lot of RAM. Which method are you using? Regards . ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [November 4, 2014, 9:17pm UTC](https://forums.freertos.org/t/pic32mz-assert-exception-in-vlistinsertend/1942/5 "2014-11-04T21:17:16Z")
**[jmmag](https://sourceforge.net/u/jmmag/)** wrote on [Tuesday, November 04, 2014](https://sourceforge.net/p/freertos/discussion/382005/thread/5874244d/#543e): I am using the latter method of wrapping the InterruptHandler into the assembly InterruptWrapper just like all of the demos supplied by FreeRTOS & Microchip. Another point worth mentioning is that the issue goes away when I decrease the interrupt frequency. Is it possible for an ISR to yield to its own interrupt if one happens before portEND\_SWITCHING\_ISR() exits? Perhaps I shouldn’t be clearing the interrupt flag until I know _for sure_ that the ISR has exited. ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [November 5, 2014, 5:09am UTC](https://forums.freertos.org/t/pic32mz-assert-exception-in-vlistinsertend/1942/6 "2014-11-05T05:09:52Z")
**[rtel](https://sourceforge.net/u/rtel/)** wrote on [Wednesday, November 05, 2014](https://sourceforge.net/p/freertos/discussion/382005/thread/5874244d/#543e/200e): On a lot of architectures it would not be possible for an ISR to yield to its own interrupt, but I’m not sure on the MIPs. It depends on the interrupt controller implementation.