PIC 18F6527

pietro77 wrote on Wednesday, July 18, 2007:

Hi all, I’m going to use freeRTOS on pic18F6527 (8722 family) and I noticed that its port is suitable only on pic18F452.
I would like to know where can I find any suggetions for this port or, better, even if anyone tried this port before.

Thank you in advance,


davedoors wrote on Wednesday, July 18, 2007:

Other than ROM/RAM sizes, what are the differences between the two devices?

pietro77 wrote on Wednesday, July 18, 2007:

There are a lot of differences, if we are speaking about 18f452 e i8f6527 these can be summarized as follow:


High Performance RISC CPU:
• C compiler optimized architecture/instruction set
- Source code compatible with the PIC16 and PIC17 instruction sets
• Linear program memory addressing to 32 Kbytes
• Linear data memory addressing to 1.5 Kbytes
• Up to 10 MIPs operation:
- DC - 40 MHz osc./clock input
- 4 MHz - 10 MHz osc./clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 8 x 8 Single Cycle Hardware Multiplier

Peripheral Features:
• High current sink/source 25 mA/25 mA
• Three external interrupt pins
• Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter with 8-bit period register (time-base for PWM)
• Timer3 module: 16-bit timer/counter
• Secondary oscillator clock option - Timer1/Timer3
• Two Capture/Compare/PWM (CCP) modules.

CCP pins that can be configured as:
- Capture input: capture is 16-bit,max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit,
max. PWM freq. @: 8-bit resolution = 156 kHz 10-bit resolution = 39 kHz
• Master Synchronous Serial Port (MSSP) module,

Two modes of operation:
- 3-wire SPI™ (supports all 4 SPI modes)
- I2C™ Master and Slave mode

Peripheral Features (Continued):
• Addressable USART module:
- Supports RS-485 and RS-232
• Parallel Slave Port (PSP) module

Analog Features:
• Compatible 10-bit Analog-to-Digital Converter module (A/D) with:
- Fast sampling rate
- Conversion available during SLEEP
- Linearity ≤ 1 LSb
• Programmable Low Voltage Detection (PLVD)
- Supports interrupt on-Low Voltage Detection
• Programmable Brown-out Reset (BOR)

Special Microcontroller Features:
• 100,000 erase/write cycle Enhanced FLASH program memory typical
• 1,000,000 erase/write cycle Data EEPROM memory
• FLASH/Data EEPROM Retention: > 40 years
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own On-Chip RC Oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• Single supply 5V In-Circuit Serial Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins

CMOS Technology:
• Low power, high speed FLASH/EEPROM technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption:
- < 1.6 mA typical @ 5V, 4 MHz
- 25 μA typical @ 3V, 32 kHz
- < 0.2 μA typical standby current


Peripheral Highlights:
• Two Master Synchronous Serial Port (MSSP) modules supporting 2/3/4-wire SPI™ (all 4 modes) and I2C™ Master and Slave modes
• Two Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP) modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
• Two Enhanced Addressable USART modules:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-Wake-up on Start bit
- Auto-Baud Detect
• 10-bit, up to 16-channel Analog-to-Digital Converter module (A/D)
- Auto-acquisition capability
- Conversion available during Sleep
• Dual analog comparators with input multiplexing
• High-current sink/source 25 mA/25 mA
• Four programmable external interrupts
• Four input change interrupts External Memory Interface (PIC18F8527/8622/8627/8722 only):
• Address capability of up to 2 Mbytes
• 8-bit or 16-bit interface
• 8, 12, 16 and 20-bit Address modes

Power-Managed Modes:
• Run: CPU on, peripherals on
• Idle: CPU off, peripherals on
• Sleep: CPU off, peripherals off
• Idle mode currents down to 15 μA typical
• Sleep current down to 0.2 μA typical
• Timer1 Oscillator: 1.8 μA, 32 kHz, 2V
• Watchdog Timer: 2.1 μA

Special Microcontroller Features:
• C compiler optimized architecture:
- Optional extended instruction set designed to optimize re-entrant code
• 100,000 erase/write cycle Enhanced Flash program memory typical
• 1,000,000 erase/write cycle Data EEPROM memory typical
• Flash/Data EEPROM Retention: 100 years typical
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V
• Fail-Safe Clock Monitor
• Two-Speed Oscillator Start-up
• nanoWatt

These informations are taken directly by the respective datasheets.

Any suggestion will be welcomed :slight_smile:

Thank you in advance,


davedoors wrote on Thursday, July 19, 2007:

C compiler optimized architecture?  That’s funny.

FreeRTOS only cares about the register set and timers.  I was meaning are there any differences to the cores?  Do they share the same register set?  If so then the two are ‘compatible’.  Maybe if the timers are different then a different timer would have to be chosen to generate the tick?

paul_piak wrote on Tuesday, July 31, 2007:


Don’t worry about the peripherals, the instruction set of the processors are the same, so you can use it. I have been using freertos on the 8525 and the 8627 without problems.
Just be sure to disable ‘extended’ mode in the compiler options, as this (when checked) activates the ‘c-optimized instructions’. These allow more efficient translation from C to machine instructions (indirect access with offset, etc.) but the context save/restore routines should be changed for this to work because the mathdata and tempdata are on different locations then. Save this for later.

Be sure to follow the PIC18 instructions on the freertos website to modify the mathdata and tempdata save/restore sections in port.c

Good luck,

Paul van der Hulst