anonymous wrote on Sunday, December 20, 2009:
Use of multiple memories minimizes clock cycles to execute C statements and expressions. The design is being implemented in a software emulator that produces a cycle log showing the flow of variables.
Here’s an opportunity to help hone the RTOS timing since the registers won’t have to be stacked, only the controls.
The interrupt mechanism has not yet been designed. The architecture can be tuned to RTOS functions.