# Memory Management on ARM CORTEX-A9 **URL:** \ **Category:** Xilinx\ **Created:** [April 14, 2023, 4:14pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226 "2023-04-14T16:14:36Z")\ **Posts on this page:** 14\ **Page:** 1
**Author:** ![dougr](https://avatars.discourse-cdn.com/v4/letter/d/ebca7d/32.png) [@dougr](https://forums.freertos.org/u/dougr)\ **Post date:** [April 14, 2023, 4:14pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/1 "2023-04-14T16:14:36Z")
Hi all, I’m trying to get a DMA engine to access main memory on a Xilinx Zynq 7000 (ARM Cortex-A9). I’m setting the source address for the DMA engine to the start address of the array in memory. However, I’m getting bad data passed to the destination. I understand there is no memory management in FreeRTOS, but the ARM does have a memory management unit and I read some conflicting reports on this. Do I need to get a physical address for the DMA source address somehow? ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [April 14, 2023, 4:44pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/2 "2023-04-14T16:44:37Z")
It is unlikely the MMU is in use if FreeRTOS is running on the device, so as far as I know, physical addresses are all you have. ---
**Author:** ![dougr](https://avatars.discourse-cdn.com/v4/letter/d/ebca7d/32.png) [@dougr](https://forums.freertos.org/u/dougr)\ **Post date:** [April 14, 2023, 6:05pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/3 "2023-04-14T18:05:41Z")
Thanks, Richard. I have this code: ```auto uint32_t E1vector[2160]; E1vector = (uint32_t *)malloc(2160*sizeof(uint32_t)); wdata = (uint32_t)&E1vector; cdma0_srcaddr_wr(wdata); ``` I can breakpoint on the wdata assignment and see the what the address is, butI can’t read the elf file in Vitis to determine if it’s correct. I know my overall programming of the DMA is correct because if I transfer the array to BRAM, it works. ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [April 14, 2023, 6:29pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/4 "2023-04-14T18:29:21Z")
The map file, generated by the linker, should give you valid address ranges. Does the DMA work in a bare metal application (without FreeRTOS)? ---
**Author:** ![dougr](https://avatars.discourse-cdn.com/v4/letter/d/ebca7d/32.png) [@dougr](https://forums.freertos.org/u/dougr)\ **Post date:** [April 14, 2023, 6:42pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/5 "2023-04-14T18:42:41Z")
I don’t see a map file from Vitis. It must be there, but I don’t see it. I haven’t tried this in bare metal. ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [April 14, 2023, 8:21pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/6 "2023-04-14T20:21:28Z")
If I recall correctly the -Mmap command line option to GCC is used to generate a map, if there isn’t a check box for this in Vitis. You may need to supply a filename too, not sure. I recommend trying bare metal too as a quick way to know if there is something to do with FreeRTOS’s used of the interrupt controller or not. If it is, I recommend setting up the DMA after starting the FreeRTOS scheduler. ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [April 16, 2023, 3:56pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/7 "2023-04-16T15:56:20Z")
> [@dougr](#): > > ```auto > uint32_t E1vector[2160]; > E1vector = (uint32_t *)malloc(2160*sizeof(uint32_t)); > wdata = (uint32_t)&E1vector; > cdma0_srcaddr_wr(wdata); > > ``` This code snippet does not seem correct to me or am I missing something? Should it not be: ```auto uint32_t * E1vector = (uint32_t *)malloc(2160*sizeof(uint32_t)); cdma0_srcaddr_wr( (uint32_t)E1vector ); /* Added the explicit cast because I assume this function takes a uint32_t. */ ``` ---
**Author:** ![dougr](https://avatars.discourse-cdn.com/v4/letter/d/ebca7d/32.png) [@dougr](https://forums.freertos.org/u/dougr)\ **Post date:** [April 19, 2023, 1:51pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/8 "2023-04-19T13:51:54Z")
I tried this in bare metal and the results are the same. There must be a mapping occurring when going through the S\_AXI\_HP0 port on the Zynq PS. ---
**Author:** ![dougr](https://avatars.discourse-cdn.com/v4/letter/d/ebca7d/32.png) [@dougr](https://forums.freertos.org/u/dougr)\ **Post date:** [April 19, 2023, 1:53pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/9 "2023-04-19T13:53:04Z")
I tried your code and it hangs the system. I needed to add “&” to E1vector so it doesn’t hang. But, it still doesn’t work. ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [April 19, 2023, 4:15pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/10 "2023-04-19T16:15:02Z")
> [@dougr](#): > > I tried your code and it hangs the system. Can you break in the debugger and see what it is doing when it appears hang? > [@dougr](#): > > I needed to add “&” to E1vector so it doesn’t hang. But, it still doesn’t work. What is the signature of `cdma0_srcaddr_wr` and what does it expect? ---
**Author:** ![dougr](https://avatars.discourse-cdn.com/v4/letter/d/ebca7d/32.png) [@dougr](https://forums.freertos.org/u/dougr)\ **Post date:** [April 19, 2023, 7:34pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/11 "2023-04-19T19:34:04Z")
Okay, after a lot of digging around, I got it to work with these changes: ```auto volatile uint32_t E1vector[2160] __attribute__ ((aligned(32))); wdata = (uint32_t)E1vector; cdma0_srcaddr_wr(wdata); Xil_DCacheDisable(); ``` I think the data cache disable is the main reason it is working. I’m hoping this doesn’t hurt performance too much! ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [April 20, 2023, 3:37am UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/12 "2023-04-20T03:37:29Z")
Thank you for reporting back. ---
**Author:** ![walterz](https://avatars.discourse-cdn.com/v4/letter/w/958977/32.png) [@walterz](https://forums.freertos.org/u/walterz)\ **Post date:** [May 11, 2023, 6:18pm UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/13 "2023-05-11T18:18:03Z")
It is possible to mark areas of memory as non-cacheable in 1 Meg blocks (aligned on 1 Meg boundaries. The call is Xil\_SetTlbAttributes(), declared in xil\_mmu.h, that header also defines some of the options; I have used DEVICE\_MEMORY successfully to share memory between a cpu & a dma, but there are many other options and what you need depending upon what bus the dma is connected to. This code is cribbed with minor variations from the Zynq network interface port for FreeRTOS+TCP: #define UNCACHED\_MEMORY\_SIZE 0x100000ul static uint8\_t uncached\_mem[UNCACHED\_MEMORY\_SIZE] **attribute** ((aligned (UNCACHED\_MEMORY\_SIZE))); Xil\_SetTlbAttributes( ( uint32\_t )(&uncached\_mem[0]), DEVICE\_MEMORY); ---
**Author:** ![dougr](https://avatars.discourse-cdn.com/v4/letter/d/ebca7d/32.png) [@dougr](https://forums.freertos.org/u/dougr)\ **Post date:** [May 26, 2023, 10:54am UTC](https://forums.freertos.org/t/memory-management-on-arm-cortex-a9/17226/14 "2023-05-26T10:54:50Z")
Thanks, Walter. I’ll have to try this.