The user manula says the following regarding the CCLKSEL bits in the CCLKCFG register:
Selects the divide value for creating the CPU clock (CCLK) from the
Only 0 and odd values (1, 3, 5, …, 255) are supported and can be
used when programming the CCLKSEL bits.
Warning: Using an even value (2, 4, 6, …, 254) when setting the
CCLKSEL bits may result in incorrect operation of the device.
Yet the eclipse demo application states a value of 4 this must be incorrect?