I have a USART with byte received interrupt enabled. When a byte is arrived, I put it in a queue. I have a single task that reads that queue. Zero ticks delays in the queue receive. The problem is that I get overun error in the USART. That means the ISR routine is not running properly. And some r…

I agree with @RAc that there must be something else going on. At least when using the more optimized variant with your own circular buffer and just signaling data availability to a task (as recommended using a task notification or a semaphore) and flushing all available data in the task when woken …

[image] hs2: Is there really no other fast firing interrupt enabled and the SysTick interrupt prio is set to default (lowest) ? Interrupt nesting is also enabled ? Interrupt nesting is enabled by setting different priorities on NVIC. I did not change anything on the SysTick priorities.

[image] hs2: This should easily work with your MCU running at 120 MHz. And I think also the simple byte-by-byte transfer with a queue or stream buffer should work reliably. With the same MCU. I have attempted to read bytes from USART while core works at 12MHz and it was working fine without a…

The only thing I can think of to help you would be to ask you for your implementations of the critical section API. Other than that, Tracealyzer is your friend…

That’s what I’d expected. I’m using an even lower CPU clock in an FreeRTOS application and also handle a USART and other peripherals reliably. This brings us back to the question what’s going on here :thinking: Strange… NVIC prio grouping is disabled, too ? Using NVIC_SetPriorityGrouping(0); BTW …

what are your port’s custom implementations of EnterCriticalSection and LeaveCriticalSection (or what those are called)?

void vPortEnterCritical( void ) { portDISABLE_INTERRUPTS(); uxCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so * assert() if it is being called from an interrupt context. Only API * functions that end in "FromISR" can be used in a…

Do you use the FPU and the ‘CM4F’ port or the normal ‘CM3’ port ?

The normal CM3 port. My chip does not have FPU

ISR routine is not properly running

Kernel

hs2 (Hartmut Schaefer) August 19, 2023, 6:08pm 39

You’re right
Me and many others found this post pretty good

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ISR routine is not properly running

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