#define configENABLE_FPU 1
#define configENABLE_MPU 0
#define configUSE_PREEMPTION 1
#define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES ( 56 )
#define configMINIMAL_STACK_SIZE ((uint16_t)128)
#define configTOTAL_HEAP_SIZE ((size_t)20480)
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_COUNTING_SEMAPHORES 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
ISR contents:
if(LL_USART_IsActiveFlag_IDLE(USART3))
{
LL_USART_ClearFlag_IDLE(USART3);
READ_REG(USART3->ISR);
READ_REG(USART3->RDR);
LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_8);
LL_USART_DisableDMAReq_RX(USART3);
Bus1.PhyConnect.RxLen=sizeof(Bus1.PhyConnect.RxBuf)-
LL_DMA_GetDataLength(DMA1,LL_DMA_CHANNEL_8);
uint32_t xResult = osEventFlagsSet(myEvent01Handle, (1<<BUS1_RXED));
if(xResult )
ch26pin_toggle();
}
TaskB contents:
osThreadId_t TaskB_TaskHandle;
const osThreadAttr_t TaskB_Task_attributes = {
.name = "Bus1_Task",
.priority = (osPriority_t) osPriorityNormal3,
.stack_size = 256 * 4
};
void TaskB(void *argument)
{
/* USER CODE BEGIN 5 */
uint32_t bus1Flag;
/* Infinite loop */
for(;;)
{
bus1Flag = osEventFlagsWait(myEvent01Handle, (1<<BUS1_RXED), osFlagsWaitAny, osWaitForever);
if(bus1Flag & (1<<BUS1_RXED))
{
ch25pin_toggle();
//BusX_Packet_Parse(&Bus1);
}
}
/* USER CODE END 5 */
}
TaskA contents:
osThreadId_t defaultTaskHandle;
const osThreadAttr_t defaultTask_attributes = {
.name = "defaultTask",
.priority = (osPriority_t) osPriorityNormal,
.stack_size = 256 * 4
};
void StartDefaultTask(void *argument)
{
/* USER CODE BEGIN 5 */
Bus1TaskInit();
/* Infinite loop */
for(;;)
{
osDelay(10);
Attitude_Calculation();//it takes about 5ms，can be Replaced with **HAL_Delay(5);**
}
/* USER CODE END 5 */
}
you can see there is a delay betweent CH25 and CH26(A1~A2).
Thanks