# Has anybody ported FreeRtos on S3C4510B? **URL:** \ **Category:** Kernel\ **Created:** [August 7, 2008, 6:49am UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084 "2008-08-07T06:49:53Z")\ **Posts on this page:** 12\ **Page:** 1
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [August 7, 2008, 6:49am UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/1 "2008-08-07T06:49:53Z")
**[aeyes](https://sourceforge.net/u/aeyes/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f): Hi ,     I am trying to port FreeRoos on Samsung S3C4510 b , skyeye simulator . I am using the existing LPC2106 port as it also has a standard ARM7TDMI core . I made the necessary changes to the timer in the prvsetuptimer function specific to Samsung .   The application starts , I know this because I have put checkpoints at various sectonsof the RTOS code, but then it hangs somewhere . I am unable to trace where it hangs .   Please note I have not used a hardware yet for this port. Has anyone ported FreeRtos on this processor ? Please advise . Regards   ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [August 7, 2008, 8:01am UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/2 "2008-08-07T08:01:58Z")
**[rtel](https://sourceforge.net/u/rtel/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/3193): Also check your startup code.  You need a stack for Supervisor and IRQ modes as a minimum, and you need to call main() from Supervisor mode. I don’t know how accurate the SkyEye simulator is but I know there are other people using it. Regards. ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [August 7, 2008, 9:24am UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/3 "2008-08-07T09:24:39Z")
**[aeyes](https://sourceforge.net/u/aeyes/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/ef61): Hi Richard , Thanks a lot . I will paste the stsrtup file for your reference . The first problem is that the interrupts are not gettign disabled somehow when the code enters the main . It could be a simulator problem , I have posted a mail at the skyeye forum too regarding this . Also I have edited only the prvsetuptimer function of the code to accomodate the S3C4510b timer . I have given an arbitrary delay for the timer which is a long one . The timer setup is fine as I have checked running the timer on the simulator . Also I put a endless for loop at the end of the code on prvtimer setup to check if the timer is running , and the timer runs. Also S3C4510b hass a non vectored interrupt structure so I have dedicated the IRQ interrupt request for the timer interrupt, so at the IRQ ISR I have given a branch to the tick ISR routine directly . I have removed the naked attribute and handling the return from interrupt at the assembly level itself . I am using the Yagarto GNU compiler. I am setting upma stack for the Supervisor and IRQ modes in the startup . I have borrowed the stsrtup routing from somewhere and made the necessary changes. I am creatijgn2 tasks and trying to run them , the code starts running as I have put various check points in the RTOS source which sends characters out through the UART to indicate a particular section of the code has been reaches, but I am unable to trace it to where it finally hangs. Also since I am new to embedded development on the whole , I have issues in running GDB and getting a stack dump , but I am working on it . Pasting the startup code below for you to have a look . Please note that just before the branch to the main routine I have moved to the supervisor mode and disabled the interrupts , but still the interrupts did not get disabled. Thank you . /\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/ /\*  crt.S \*/ /\* S3C4510 \*/ /\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*/ @ .include "S3C4510.mac" .EQU LOCKOUT, 0xC0 .EQU MODE\_MASK, 0x1F .EQU UDF\_MODE, 0x1B .EQU ABT\_MODE, 0x17 .EQU SUP\_MODE, 0x13 @ SVC .EQU IRQ\_MODE, 0x12 @  IRQ .EQU FIQ\_MODE, 0x11 @  FIQ .EQU USR\_MODE, 0x10 @ USR .equ I\_BIT, 0x80 /\* when I bit is set, IRQ is disabled \*/ .equ F\_BIT, 0x40 /\* when F bit is set, FIQ is disabled \*/ .set MODE\_SVC, 0x13 /\* Supervisor Mode \*/ ENTRY: B Reset\_Handler B SystemUndefinedHandler B SystemSwiHandler B SystemPrefetchHandler B SystemAbortHandler B SystemReserv B SystemIrqHandler B SystemFiqHandler .global Reset\_Handler Reset\_Handler: LDR r0, =0x3FF0000 LDR r1, =0xe7ffff90 STR r1, [r0] LDR r0, =0x3ff3008 LDR r1, =0x6000000 @ Trying to configure EXTACON0 with tACC1 = 5 cycles STR r1, [r0] .ifdef ROM LDR r0, =SystemInitDataSDRAM LDMIA r0, {r1-r12} LDR r0, =0x3FF0000 + 0x3010 STMIA r0, {r1-r12} .endif .extern Image\_RO\_Limit .extern Image\_RW\_Base .extern Image\_ZI\_Base .extern Image\_ZI\_Limit LDR r0, =Image\_RO\_Limit LDR r1, =Image\_RW\_Base LDR r3, =Image\_ZI\_Base CMP r0, r1 BEQ LOOP1 LOOP0: CMP r1, r3 LDRCC r2, [r0], #4 STRCC r2, [r1], #4 BCC LOOP0 LOOP1: LDR r1, =Image\_ZI\_Limit MOV r2, #0 LOOP2: CMP r3, r1 STRCC r2, [r3], #4 BCC LOOP2 INITIALIZE\_STACK: MRS r0, cpsr BIC r0, r0, #LOCKOUT | MODE\_MASK ORR r2, r0, #USR\_MODE ORR r1, r0, #LOCKOUT | FIQ\_MODE MSR cpsr\_cf, r1 MSR spsr\_cf, r2 LDR sp, =FIQ\_STACK ORR r1, r0, #LOCKOUT | IRQ\_MODE MSR cpsr\_cf, r1 MSR spsr\_cf, r2 LDR sp, =IRQ\_STACK ORR r1, r0, #LOCKOUT | ABT\_MODE MSR cpsr\_cf, r1 MSR spsr\_cf, r2 LDR sp, =ABT\_STACK ORR r1, r0, #LOCKOUT | UDF\_MODE MSR cpsr\_cf, r1 MSR spsr\_cf, r2 LDR sp, =UDF\_STACK ORR r1, r0, #LOCKOUT | SUP\_MODE MSR cpsr\_cf, r1 MSR spsr\_cf, r2 LDR sp, =SUP\_STACK MRS r0, cpsr BIC r0, r0, #LOCKOUT | MODE\_MASK ORR r1, r0, #USR\_MODE MSR cpsr\_cf, r0 LDR sp, =USR\_STACK msr CPSR\_c, #MODE\_SVC|I\_BIT|F\_BIT    # this is where I have tried to disable the IRQ and FIQ ISR but it has no effect ☹ … .extern main BL main SystemUndefinedHandler: B SystemUndefinedHandler SystemSwiHandler: B SystemSwiHandler MakeSVC: B MakeSVC SystemPrefetchHandler: B SystemPrefetchHandler SystemAbortHandler: B SystemAbortHandler SystemReserv: B SystemReserv SystemIrqHandler: .extern ISR\_IrqHandler STMFD sp!, {r0-r12, lr} BL ISR\_IrqHandler LDMFD sp!, {r0-r12, lr} SUBS pc, lr, #4 SystemFiqHandler: .extern ISR\_FiqHandler STMFD sp!, {r0-r7, lr} BL ISR\_FiqHandler LDMFD sp!, {r0-r7, lr} SUBS pc, lr, #4 SystemInitDataSDRAM: .long 0x0a7fff0f @;EXTDBWTH #.long 0x01000060 @;ROMCON0 .long 0x02000060 @;ROMCON0 #.long 0x13044060 @;ROMCON1 .long 0x22080060 @;ROMCON1 .long 0x00000060 @;ROMCON2 .long 0x00000060 @;ROMCON3 .long 0x00000060 @;ROMCON4 .long 0x00000060 @;ROMCON5 .long 0x11004380 @;DRAMCON0 #.long 0x20040380 @;DRAMCON0 .long 0x00000000 @;DRAMCON1 .long 0x00000000 @;DRAMCON2 .long 0x00000000 @;DRAMCON3 .long 0xce278360 @;REFEXTCON # .long 0x00003E02 @ EXTDBWTH # .long 0x02000060 @ ROMCOON0 0~0x200000 # .long 0x40010040 # .long 0x00000060 # .long 0x00000060 # .long 0x00000060 # .long 0x00000060 # .long 0x14010301 # .long 0x00000000 # .long 0x00000000 # .long 0x00000000 # .long 0x9C298360 .data .SPACE 1024 USR\_STACK: .SPACE 512 UDF\_STACK: .SPACE 512 ABT\_STACK: .SPACE 512 IRQ\_STACK: .SPACE 512 FIQ\_STACK: .SPACE 512 SUP\_STACK: ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [August 7, 2008, 9:28am UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/4 "2008-08-07T09:28:27Z")
**[aeyes](https://sourceforge.net/u/aeyes/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/dd8b): Oops please note at the call to the IRQ handler the commands that you see here for saving the registers and restoring them have actually been removed , this is a slightly older script, actually I am expecting that the save and restore context will do the job so I do not need it here I have just retained the SUBS pc, lr, #4 in the IRQ handler routine as I have declared the tick ISR as just a function . That is I have removed the naked and the -attribute - notations . Regards ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [August 7, 2008, 11:55am UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/5 "2008-08-07T11:55:42Z")
**[aeyes](https://sourceforge.net/u/aeyes/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/9b1c): Also for this section in the startup script above .extern ISR\_FiqHandler  STMFD sp!, {r0-r7, lr}  BL ISR\_FiqHandler  LDMFD sp!, {r0-r7, lr}  SUBS pc, lr, #4  Please read it as .extern vTickISR BL vTickISR SUBS pc, lr, #4  and the finction void vTickISR( void ) \_\_attribute\_\_((naked)) has been changed to void vTickISR( void ) and of course I have cleared the S3C4510 interrupt flag once I got into the function. Regards ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [August 7, 2008, 3:42pm UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/6 "2008-08-07T15:42:11Z")
**[aeyes](https://sourceforge.net/u/aeyes/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/9a66): Tried allocating stack space in supervisor mode , still no avail ☹ … I have to do a stack trace … ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [August 7, 2008, 4:09pm UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/7 "2008-08-07T16:09:33Z")
**[aeyes](https://sourceforge.net/u/aeyes/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/40cb): Also I altered the order of the makefile and placed the stsrtup code to start fron 0x00000000 , in LPC2106 port the startup code is placed elsewhere . Why was the startup code linked at the end in the case of LPC2106 ? ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [August 7, 2008, 4:15pm UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/8 "2008-08-07T16:15:05Z")
**[rtel](https://sourceforge.net/u/rtel/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/ef61/afa9): \> Also I have edited only the prvsetuptimer function of the \> Also S3C4510b hass a non vectored interrupt structure so I \> have dedicated the IRQ interrupt request for the timer \> interrupt, When you come to do the real code you can do the save and restore of the context from the single interrupt entry point.  There are examples of doing this in the [FreeRTOS.org](http://FreeRTOS.org) download.  I think the IAR STR9 demo does this. Regards. ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [August 7, 2008, 4:16pm UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/9 "2008-08-07T16:16:39Z")
**[rtel](https://sourceforge.net/u/rtel/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/9b1c/652c): \> Also for this section in the startup script above \> \> .extern ISR\_FiqHandler  Are you using the FIQ interrupt?  Best not to do this, at least until you have a simple system up and running. Regards. ---
**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\ **Post date:** [August 7, 2008, 4:18pm UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/10 "2008-08-07T16:18:13Z")
**[rtel](https://sourceforge.net/u/rtel/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/40cb/2f2c): You need to setup the linker script to be correct for whatever your processor has configured.  Some processors allow remapping, for example so the vector table can be in RAM.  Regards. ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [August 7, 2008, 5:26pm UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/11 "2008-08-07T17:26:03Z")
**[aeyes](https://sourceforge.net/u/aeyes/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/f55b): I have this linker script for the processor SECTIONS {     . = 0x00000000;     Image\_RO\_Base = .;     .text : { \*(.text) }     .rodata : { \*(.rodata) }     Image\_RO\_Limit = .;     . = 0x01000000;      Image\_RW\_Base = .;     .data : { \*(.data) }     Image\_RW\_Limit = .;     Image\_ZI\_Base = .;     .bss : { \*(.bss) }     Image\_ZI\_Limit = .;     end = .;     .debug\_info     0 : { \*(.debug\_info)  }      .debug\_line        0 : { \*(.debug\_line)  }        .debug\_abbrev   0 : { \*(.debug\_abbrev)}        .debug\_frame    0 : { \*(.debug\_frame) } } and this is my makefile which I have referred from the LPC2106 port , I have only changed the sequence of linking of the startup file the interrupt vectors are not remapped in this case . CC=arm-elf-gcc OBJCOPY=arm-elf-objcopy ARCH=arm-elf-ar CRT0=crt.s WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare         -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused # # CFLAGS common to both the THUMB and ARM mode builds # CFLAGS=$(WARNINGS) -D $(RUN\_MODE) -D GCC\_ARM7 -I. -I…/…/Source/include         -I…/Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT)          $(OPTIM) -fomit-frame-pointer -fno-strict-aliasing ifeq ($(USE\_THUMB\_MODE),YES)     CFLAGS += -mthumb-interwork -D THUMB\_INTERWORK     THUMB\_FLAGS=-mthumb endif LINKER\_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map RTOS\_SOURCE\_DIR=…/…/Source DEMO\_SOURCE\_DIR=…/Common/Minimal # # Source files that can be built to THUMB mode. # THUMB\_SRC = hello.c serial/serial.c ParTest/ParTest.c $(DEMO\_SOURCE\_DIR)/integer.c $(DEMO\_SOURCE\_DIR)/flash.c $(DEMO\_SOURCE\_DIR)/PollQ.c $(DEMO\_SOURCE\_DIR)/comtest.c $(DEMO\_SOURCE\_DIR)/flop.c $(DEMO\_SOURCE\_DIR)/semtest.c $(DEMO\_SOURCE\_DIR)/dynamic.c $(DEMO\_SOURCE\_DIR)/BlockQ.c $(RTOS\_SOURCE\_DIR)/tasks.c $(RTOS\_SOURCE\_DIR)/queue.c $(RTOS\_SOURCE\_DIR)/list.c $(RTOS\_SOURCE\_DIR)/portable/MemMang/heap\_2.c $(RTOS\_SOURCE\_DIR)/portable/GCC/ARM7\_LPC2000/port.c # # Source files that must be built to ARM mode. # ARM\_SRC = $(RTOS\_SOURCE\_DIR)/portable/GCC/ARM7\_LPC2000/portISR.c serial/serialISR.c # # Define all object files. # ARM\_OBJ = $(ARM\_SRC:.c=.o) THUMB\_OBJ = $(THUMB\_SRC:.c=.o) rtosdemo.hex : rtosdemo.elf     $(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex rtosdemo.elf :$(CRT0) $(ARM\_OBJ) $(THUMB\_OBJ) Makefile     $(CC) $(CFLAGS) -nostartfiles $(CRT0) $(ARM\_OBJ) $(THUMB\_OBJ)  $(LINKER\_FLAGS) $(THUMB\_OBJ) : %.o : %.c $(LDSCRIPT) Makefile     $(CC) -c -g $(THUMB\_FLAGS) $(CFLAGS) $\< -o $@ $(ARM\_OBJ) : %.o : %.c $(LDSCRIPT) Makefile     $(CC) -c -g $(CFLAGS) $\< -o $@ clean :     touch Makefile I am using the rom\_arm.bat to compile … the linker thus shown is working because I have compiled sinpler codes with the same linker and run them. Here is the batch file from the LPC2106 port where I have altered the linker script file to be my file and stopped the optimisation . set USE\_THUMB\_MODE=NO set DEBUG= set OPTIM=-O0 set RUN\_MODE=RUN\_FROM\_ROM set LDSCRIPT=FLASH.LD make ---
**Author:** ![system](https://d2v6vdsk2p900z.cloudfront.net/original/1X/7fc8fdb729c645aab5b20282bbe34e57cb407be6.jpeg) [@system](https://forums.freertos.org/u/system)\ **Post date:** [August 7, 2008, 5:30pm UTC](https://forums.freertos.org/t/has-anybody-ported-freertos-on-s3c4510b/5084/12 "2008-08-07T17:30:27Z")
**[aeyes](https://sourceforge.net/u/aeyes/)** wrote on [Thursday, August 07, 2008](https://sourceforge.net/p/freertos/discussion/382005/thread/e1aa8c0b/#bd8f/1108): No I have left the fiq interrupt as of now I have not touched it , I am working with only the IRQ…