# HardFault randomly in xEventGroupWaitBits **URL:** \ **Category:** Kernel\ **Created:** [October 3, 2024, 11:23am UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567 "2024-10-03T11:23:14Z")\ **Posts on this page:** 20\ **Page:** 1
**Author:** ![rickou](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rickou/32/4951_2.png) [@rickou](https://forums.freertos.org/u/rickou)\ **Post date:** [October 3, 2024, 11:23am UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/1 "2024-10-03T11:23:15Z")
hi there ! since i use Cellular interface lib, i get randomly some hardfault always at the same place (xEventGroupWaitBits) deeply called from Cellular\_Init() ![image](https://d2v6vdsk2p900z.cloudfront.net/original/2X/4/4f28fc81643e7bcd68e5a3ef911017475ffa2159.png) ---
**Author:** ![rickou](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rickou/32/4951_2.png) [@rickou](https://forums.freertos.org/u/rickou)\ **Post date:** [October 3, 2024, 11:23am UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/2 "2024-10-03T11:23:52Z")
I think the random effect is due to timing, but i’m not sure… I tryed to investiguate, and i found the fault happen when executing listINSERT\_END( pxEventList, &( pxCurrentTCB-\>xEventListItem ) ); inside the function vTaskPlaceOnUnorderedEventList checking the variables, i think the problem is due to pxEventList.pxIndex is NULL ? ![image](https://d2v6vdsk2p900z.cloudfront.net/original/2X/0/0bdd9ea6d78116ee769fc2d9600aa41378eba78f.png) ---
**Author:** ![rickou](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rickou/32/4951_2.png) [@rickou](https://forums.freertos.org/u/rickou)\ **Post date:** [October 3, 2024, 11:24am UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/3 "2024-10-03T11:24:59Z")
The assembly is stopped here but no code is detailled due to the Macro ![image](https://d2v6vdsk2p900z.cloudfront.net/original/2X/8/83fdf99f89c237a5f4ab5ea8955692006e08c1b2.png) so, i do not understand what could be wrong… most of time, it works like a charm… PS: Sorry for multiple posting, but i’m not able to put 3 screenshot in 1 post… (bad rule) ---
**Author:** ![hs2](https://avatars.discourse-cdn.com/v4/letter/h/a4c791/32.png) [@hs2](https://forums.freertos.org/u/hs2)\ **Post date:** [October 3, 2024, 12:04pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/4 "2024-10-03T12:04:22Z")
Memory corruption due to stack overflow ? Did you enable stack checking and define configASSERT ? ---
**Author:** ![rickou](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rickou/32/4951_2.png) [@rickou](https://forums.freertos.org/u/rickou)\ **Post date:** [October 3, 2024, 12:57pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/5 "2024-10-03T12:57:22Z")
i don’t think so, this happen very early after reset. i put the stack overflow hook function, but i need to check if i enabled the stack checking. yes configASSERT is defined. ---
**Author:** ![rickou](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rickou/32/4951_2.png) [@rickou](https://forums.freertos.org/u/rickou)\ **Post date:** [October 3, 2024, 1:00pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/6 "2024-10-03T13:00:19Z")
i do not find how to enable stack checking ? ---
**Author:** ![hs2](https://avatars.discourse-cdn.com/v4/letter/h/a4c791/32.png) [@hs2](https://forums.freertos.org/u/hs2)\ **Post date:** [October 3, 2024, 1:36pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/7 "2024-10-03T13:36:06Z")
> **[FreeRTOS stack usage and stack overflow checking - FreeRTOS™](https://www.freertos.org/Documentation/02-Kernel/02-Kernel-features/09-Memory-management/02-Stack-usage-and-stack-overflow-checking)** > > FreeRTOS stack usage and stack overflow checking ---
**Author:** ![rickou](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rickou/32/4951_2.png) [@rickou](https://forums.freertos.org/u/rickou)\ **Post date:** [October 3, 2024, 1:52pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/8 "2024-10-03T13:52:53Z")
👍 thank you just added to the config compile, run, and the random crash time is now ! but, the code still halt at same place… no ASSERT, no call to vApplicationStackOverflowHook… When running, the task that is crashing have about 30% free stack (initial 4kB) ---
**Author:** ![hs2](https://avatars.discourse-cdn.com/v4/letter/h/a4c791/32.png) [@hs2](https://forums.freertos.org/u/hs2)\ **Post date:** [October 3, 2024, 1:57pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/9 "2024-10-03T13:57:23Z")
Strange … if it’s a Cortex-M MCU a wrong interrupt priority might be a source of corruptions, too. Maybe see [Running the RTOS on a ARM Cortex-M Core - FreeRTOS™](https://www.freertos.org/Documentation/02-Kernel/03-Supported-devices/04-Demos/ARM-Cortex/RTOS-Cortex-M3-M4) Or just a normal programming bug 😉 ---
**Author:** ![rickou](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rickou/32/4951_2.png) [@rickou](https://forums.freertos.org/u/rickou)\ **Post date:** [October 3, 2024, 2:01pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/10 "2024-10-03T14:01:57Z")
yes it is a cortex-M33, i already read the article, and configASSERT is defined, so if i understand well, and if the NVIC is misconfigured, the kernel should get it… i have no doubt, the pb comes from a mistake somewhere, but because it is not each time, it is difficult to find it… ---
**Author:** ![hs2](https://avatars.discourse-cdn.com/v4/letter/h/a4c791/32.png) [@hs2](https://forums.freertos.org/u/hs2)\ **Post date:** [October 3, 2024, 2:14pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/11 "2024-10-03T14:14:04Z")
Yes - recent FreeRTOS versions catch many common problems including interrupt priority issues. Those bugs can be nasty … good luck 👍 ---
**Author:** ![rickou](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rickou/32/4951_2.png) [@rickou](https://forums.freertos.org/u/rickou)\ **Post date:** [October 3, 2024, 2:18pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/12 "2024-10-03T14:18:09Z")
I think you’re right pointing interrupt mis-configuration, because the crash comes some lines after enabling interrupts (and waiting for it firing) i reread the article… hard to well understand… could you help me to check if my interrupt config is good ? ---
**Author:** ![hs2](https://avatars.discourse-cdn.com/v4/letter/h/a4c791/32.png) [@hs2](https://forums.freertos.org/u/hs2)\ **Post date:** [October 3, 2024, 3:28pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/13 "2024-10-03T15:28:01Z")
Or do you enable interrupts before initializing the resource used in an ISR ? E.g. a queue might not been created but the ISR tries to push something in it ? As mentioned wrong interrupt priorities are catched by configASSERT by recent FreeRTOS versions… ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [October 3, 2024, 4:16pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/14 "2024-10-03T16:16:50Z")
> [@rickou](#): > > could you help me to check if my interrupt config is good ? Can you first remove this interrupt code and see if the crash goes away? [This page](https://www.freertos.org/Documentation/02-Kernel/03-Supported-devices/04-Demos/ARM-Cortex/RTOS-Cortex-M3-M4), which @hs2 already shared, provides good details about interrupt priority. What is the priority of the interrupt that you enable? Also, can you share your FreeRTOSConfig.h? ---
**Author:** ![rickou](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rickou/32/4951_2.png) [@rickou](https://forums.freertos.org/u/rickou)\ **Post date:** [October 3, 2024, 5:36pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/15 "2024-10-03T17:36:33Z")
@hs2, I only use the eventgroup inside the ISR ```auto void _HALUART_TxCpltCallback( UART_HandleTypeDef * hUart ) { BaseType_t xHigherPriorityTaskWoken = pdFALSE, xResult = pdPASS; CellularCommInterfaceContext * pIotCommIntfCtx = & _iotCommIntfCtx; if( hUart != NULL ) { xResult = xEventGroupSetBitsFromISR( pIotCommIntfCtx->pEventGroup, COMM_EVT_MASK_TX_DONE, & xHigherPriorityTaskWoken ); if( xResult == pdPASS ) { portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); } } } ``` The eventgroup is initialized earlier before the 1st sending. (before the UART is initialized) The interrupt is enabled after the UART is initialized. ```auto /* Setup the event group. */ if( ret == IOT_COMM_INTERFACE_SUCCESS ) { pIotCommIntfCtx->pEventGroup = xEventGroupCreate(); if( pIotCommIntfCtx->pEventGroup == NULL ) { LogError(( "EventGroup create failed" )); helpers_RingBufferFree(pIotCommIntfCtx->s_RxBuffer); CellularDevice_PowerOff(); ret = IOT_COMM_INTERFACE_NO_MEMORY; } } /* Setup the phy device. */ if( ret == IOT_COMM_INTERFACE_SUCCESS ) { pIotCommIntfCtx->pPhy = & _t_CommIntfPhy; ( void ) memset( pIotCommIntfCtx->pPhy, 0, sizeof( UART_HandleTypeDef ) ); if( prvCellularUartInit( pIotCommIntfCtx->pPhy ) != HAL_OK ) { LogError(( "UART init failed" )); vEventGroupDelete( pIotCommIntfCtx->pEventGroup ); helpers_RingBufferFree(pIotCommIntfCtx->s_RxBuffer); CellularDevice_PowerOff(); ret = IOT_COMM_INTERFACE_DRIVER_ERROR; } } ``` ```auto static void _HALUART_MspInitCallback(UART_HandleTypeDef *hUart) { RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; HAL_StatusTypeDef xHalStatus = HAL_OK; if( hUart != NULL ) { PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART6; PeriphClkInit.Usart6ClockSelection = RCC_USART6CLKSOURCE_SYSCLK; xHalStatus = HAL_RCCEx_PeriphCLKConfig( &PeriphClkInit ); if( xHalStatus != HAL_OK ) { LogError(( "Error while configuring peripheral clock for UART6." )); } /* Peripheral clock enable */ __HAL_RCC_USART6_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOE_CLK_ENABLE(); /* UART interrupt init */ HAL_NVIC_SetPriority (USART6_IRQn, 5, 0); HAL_NVIC_EnableIRQ(USART6_IRQn); } } ``` @aggarg, i know if i do not call the cellular interface setup, (all theses functions are not called) then all seems to works fine… because of this and the crash always happen at the same line, i’m pretty sure it is linked to the interrupt… but i also use interrupts elsewhere in the code… here is my config file. [FreeRTOSConfig.h](https://forums.freertos.org/uploads/short-url/xmtIKumPUvwsFUWeJniqRDBVKYX.h) (8.5 KB) the MCU is the STM32U5A5 and ST provide \_\_NVIC\_PRIO\_BITS set to 4 bits configKERNEL\_INTERRUPT\_PRIORITY = 0xf0 (computed value) configMAX\_SYSCALL\_INTERRUPT\_PRIORITY = 0x50 (computed value) honestly i do not remember where i get this config file (maybe in a ST example) configLIBRARY\_LOWEST\_INTERRUPT\_PRIORITY and configLIBRARY\_MAX\_SYSCALL\_INTERRUPT\_PRIORITY are not used anywhere 🤷‍♂️ the ST HAL init global init: ```auto /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); ``` the ST HAL Tick timer IRQ setup: ```auto HAL_NVIC_SetPriority(TIM6_IRQn, 0U, 0U); ``` the USB IRQ setup: ```auto HAL_NVIC_SetPriority(OTG_HS_IRQn, 6, 0); ``` the 2 OSPI IRQ setup: ```auto HAL_NVIC_SetPriority( OCTOSPI1_IRQn, 5, 0 ); ``` ```auto HAL_NVIC_SetPriority( OCTOSPI2_IRQn, 5, 0 ); ``` an external IRQ setup: (for Ethernet controller) ```auto HAL_NVIC_SetPriority( EXTI2_IRQn, 5, 0 ); ``` and the last one, for the cellular UART: (the one where the crash seems to happen) ```auto HAL_NVIC_SetPriority (USART6_IRQn, 5, 0); ``` 😱Yes clearly the IRQ priorities are set hum… using copy-paste… (except for USB) at this time it is a simple prototype, so it is good like this… i only seen the crash with the code linked to the cellular modem and few lines after using the IRQ ```auto err = HAL_UART_Transmit_IT( pIotCommIntfCtx->pPhy, ( uint8_t * ) pData, ( uint16_t ) dataLength ); if( err != HAL_BUSY ) { // Crash happen randomly always at the next line few (milli)seconds after reset // The code initialize all peripherals and starts the cellular in following inside a startup task uxBits = xEventGroupWaitBits( pIotCommIntfCtx->pEventGroup, COMM_EVT_MASK_TX_DONE | COMM_EVT_MASK_TX_ERROR | COMM_EVT_MASK_TX_ABORTED, pdTRUE, pdFALSE, pdMS_TO_TICKS( timeoutMilliseconds ) ); if( ( uxBits & ( COMM_EVT_MASK_TX_ERROR | COMM_EVT_MASK_TX_ABORTED ) ) != 0U ) { ``` thank for your help ! ---
**Author:** ![hs2](https://avatars.discourse-cdn.com/v4/letter/h/a4c791/32.png) [@hs2](https://forums.freertos.org/u/hs2)\ **Post date:** [October 3, 2024, 6:15pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/16 "2024-10-03T18:15:49Z")
Is TIM6 used as FreeRTOS tick (instead of SysTick often used by STM HAL for other purposes) ? NVIC prio 0 could be a problem b/c it’s the highest prio possible. The FreeRTOS ticker is usually set to the lowest prio. In your case it’s prio 15 then. ---
**Author:** ![kstribrn](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/kstribrn/32/2085_2.png) [@kstribrn](https://forums.freertos.org/u/kstribrn)\ **Post date:** [October 3, 2024, 8:56pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/17 "2024-10-03T20:56:36Z")
Have you set `INCLUDE_xEventGroupSetBitFromISR` in your `FreeRTOSConfig.h`? The one you’ve posted does not include this required config option. ---
**Author:** ![kstribrn](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/kstribrn/32/2085_2.png) [@kstribrn](https://forums.freertos.org/u/kstribrn)\ **Post date:** [October 3, 2024, 9:02pm UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/18 "2024-10-03T21:02:36Z")
What does your EventGroup `xTasksWaitingForBits` field look like after creation? ---
**Author:** ![rickou](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rickou/32/4951_2.png) [@rickou](https://forums.freertos.org/u/rickou)\ **Post date:** [October 4, 2024, 7:27am UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/19 "2024-10-04T07:27:17Z")
@kstribrn i searched for INCLUDE\_xEventGroupSetBitFromISR in the project, but i found no reference to it… (even in the freertos source…) 🙄 regarding the eventgroup, i think all is ok ![image](https://d2v6vdsk2p900z.cloudfront.net/original/2X/e/e757e1b584532c9d5deb85bdc93858a972007d58.png) @hs2 TIM6 is the HAL timer FreeRTOS use SysTick In addition, in CMSIS\_OS2, i found ```auto NVIC_SetPriority (SVCall_IRQn, 0U); ``` so, to summarize, i have some IRQ set to priorities 0,5 & 6 configKERNEL\_INTERRUPT\_PRIORITY sets to 15 configMAX\_SYSCALL\_INTERRUPT\_PRIORITY sets to 5 (i don’t know why) does this mean maybe my IRQ with priority 6 could be an issue ? or IRQ priority 5 could be a problem ? or i don’t understand… do i need to change the TIM6 priority? i have not found the priority of systick? ---
**Author:** ![hs2](https://avatars.discourse-cdn.com/v4/letter/h/a4c791/32.png) [@hs2](https://forums.freertos.org/u/hs2)\ **Post date:** [October 4, 2024, 7:45am UTC](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567/20 "2024-10-04T07:45:58Z")
NVIC interrupt priorities 5…15 (higher value means lower prio on Cortex-M) are allowed resp. covered by FreeRTOS means you can use FreeRTOS API calls in the corresponding ISRs. The TIM6 interrupt handler should not use FreeRTOS-API and probably doesn’t. If you’re using default SysTick for FreeRTOS tick you don’t need to care. FreeRTOS handles this for you (and set the prio to configKERNEL\_INTERRUPT\_PRIORITY). See also this posting for a pretty good explanation: > [@Understanding priority levels of ISR and FreeRTOS APIs](https://forums.freertos.org/t/understanding-priority-levels-of-isr-and-freertos-apis/10453/16): > > A pictorial representation, if that helps: Logical Numerical Priorities Priorities +--------+ +-------+ ^ | | | | | | | | | | | | | | | Not masked by FreeRTOS kernel | Higher | | Lower | | ( FreeRTOS APIs can not be | | | | | called from these ISRs. ) … [Next page](https://forums.freertos.org/t/hardfault-randomly-in-xeventgroupwaitbits/21567.md?page=2)