FreeRTOS +TCP on SAME70

Kernel
2

I’m adding some further information as I go, in the hopes that someone else looking to utilise +TCP on their SAME70-based project in the future might find it useful.

I’ve done a line-by-line review of the PHY configuration and initialisation processes, comparing the ASF lwIP-based files with +TCP. I still don’t understand why the PHY isn’t found. Below is the prvGMACInit() function, which is almost unchanged from the latest SAME70 NetworkInterface.c file:

static BaseType_t prvGMACInit( void )
{
uint32_t ncfgr;

    gmac_options_t gmac_option;

	gmac_enable_management(GMAC, true);
	/* Enable further GMAC maintenance. */
	GMAC->GMAC_NCR |= GMAC_NCR_MPE;

	memset( &gmac_option, '\0', sizeof( gmac_option ) );
	gmac_option.uc_copy_all_frame = 0;
	gmac_option.uc_no_boardcast = 0;
	memcpy( gmac_option.uc_mac_addr, ucMACAddress, sizeof( gmac_option.uc_mac_addr ) );

	gs_gmac_dev.p_hw = GMAC;
	gmac_dev_init( GMAC, &gs_gmac_dev, &gmac_option );

	NVIC_SetPriority( GMAC_IRQn, configMAC_INTERRUPT_PRIORITY );
	NVIC_EnableIRQ( GMAC_IRQn );

	{
		/* Set MDC clock divider. */
		gmac_set_mdc_clock( GMAC, sysclk_get_cpu_hz() );

		vPhyInitialise( &xPhyObject, xPHY_Read, xPHY_Write );
		while(xPhyDiscover( &xPhyObject ) < 1);
		xPhyConfigure( &xPhyObject, &xPHYProperties );

		/* For a reset / reconfigure of the EMAC. */
		prvEthernetUpdateConfig( pdTRUE );

		/* Select Media Independent Interface type */
		#if( SAME70 != 0 )
		{
			/* Selecting RMII mode. */
			GMAC->GMAC_UR &= ~GMAC_UR_RMII;
		}
		#else
		{
			gmac_select_mii_mode(GMAC, ETH_PHY_MODE);
		}
		#endif

		gmac_enable_transmit(GMAC, true);
		gmac_enable_receive(GMAC, true);

	}

	gmac_enable_management(GMAC, true);

	gmac_set_address( GMAC, 1, (uint8_t*)llmnr_mac_address );

	gmac_enable_management(GMAC, false);
	/* Disable further GMAC maintenance. */
	GMAC->GMAC_NCR &= ~GMAC_NCR_MPE;

	return 1;
}

The only change I’ve made, is putting xPhyDiscover( &xPhyObject) in a while loop, to allow for the possibility of the PHY not quite being ready. All I’ve done within xPhyDiscover() is add a printf() to monitor the value of ulLowerID from the PHY ID2 register (register 3h):

BaseTytpe_t xPhyDiscover( EthernetPhy_t *pxPhyObject)
{
BaseType_t xPhyAddress;

    pxPhyObject->xPortCount = 0;

    for( xPhyAddress = phyMIN_PHY_ADDRESS; xPhyAddress <= phyMAX_PHY_ADDRESS; xPhyAddress++ )
    {
    uint32_t ulLowerID;

        pxPhyObject->fnPhyRead( xPhyAddress, phyREG_03_PHYSID2, &ulLowerID);
        printf("phyREG_03_PHYSID2: %#08x\r\n", ulLowerID);

The resulting console output is perpetual output of the following:

phyREG_03_PHYSID2: 0x00ffff

Per Hein’s post here, I believe I have the required clocks configured and enabled, the EMAC setup hasn’t been changed from the provided SAME70 files, the pin muxing has been performed and was listed in my original post, and RMII has been selected (per the above prvGMACInit function).

Is there anything else I’m missing?