nndpkz wrote on Friday, July 06, 2018:
Hi Hein,
after some time we also tried the same thing with lwIP raw TCP/IP stack and the behavior is the same. Zynq TX side is once again the dominant one.
I started counting MAC send and receive handlers and it’s obvious that when both connections are active send handlers are completely dominant.
At one point there is:
tx_handler: 3759422
rx_handler: 864940
I will check if there are any priorities for these interrupts. I have already written to Xilinx support forum, waiting for their reply.
Best regards,
Nenad
P.S. I forgot to write that when we decreased TCP_MSS to 1024 in the FreeRTOS TCP/IP setup, that was one possible solution, but wasn’t good enough for our application.