FreeRTOS+TCP in AMD/Xilinx Vitis 2024

From my point of view it is not that simple since the XPAR_PS7_ETHERNET_0_ENET_SLCR_x_DIVx really depend on the clock settings in Vivado. Offloading this config to the embedded developer is not desirable.
My guess is that there is a different way to automatically configure this with the change to SDT based flow, I just don’t know how.