# FreeRTOS SMP with Infineon Aurix TC3xx **URL:** \ **Category:** Infineon\ **Created:** [February 21, 2024, 12:29pm UTC](https://forums.freertos.org/t/freertos-smp-with-infineon-aurix-tc3xx/19227 "2024-02-21T12:29:01Z")\ **Posts on this page:** 4\ **Page:** 1
**Author:** ![Chee2oo](https://avatars.discourse-cdn.com/v4/letter/c/e8c25b/32.png) [@Chee2oo](https://forums.freertos.org/u/Chee2oo)\ **Post date:** [February 21, 2024, 12:29pm UTC](https://forums.freertos.org/t/freertos-smp-with-infineon-aurix-tc3xx/19227/1 "2024-02-21T12:29:01Z")
Hello all, I started with my project by importing FreeRTOS v10.5.1 to an Infineon Aurix Processor. I would like to migrate my project now to v11 and use SMP. Doing so i’m getting several errors that specific ports are missing. Do you can help me out here how to implement these? | Description | Resource | Path | Location | Type | | --- | --- | --- | --- | --- | | ctc E201: #error configNUMBER\_OF\_CORES is set to more than 1 then portGET\_CORE\_ID must also be defined. | FreeRTOS.h | /ScanAndSystemController/AppSw/Tricore/OS/FreeRTOS/include | line 396 | C/C++ Problem | | ctc E201: #error configNUMBER\_OF\_CORES is set to more than 1 then portYIELD\_CORE must also be defined. | FreeRTOS.h | /ScanAndSystemController/AppSw/Tricore/OS/FreeRTOS/include | line 406 | C/C++ Problem | | ctc E201: #error portCLEAR\_INTERRUPT\_MASK is required in SMP | FreeRTOS.h | /ScanAndSystemController/AppSw/Tricore/OS/FreeRTOS/include | line 422 | C/C++ Problem | | ctc E201: #error portENTER\_CRITICAL\_FROM\_ISR is required in SMP | FreeRTOS.h | /ScanAndSystemController/AppSw/Tricore/OS/FreeRTOS/include | line 470 | C/C++ Problem | | ctc E201: #error portEXIT\_CRITICAL\_FROM\_ISR is required in SMP | FreeRTOS.h | /ScanAndSystemController/AppSw/Tricore/OS/FreeRTOS/include | line 478 | C/C++ Problem | | ctc E201: #error portGET\_ISR\_LOCK is required in SMP | FreeRTOS.h | /ScanAndSystemController/AppSw/Tricore/OS/FreeRTOS/include | line 462 | C/C++ Problem | | ctc E201: #error portGET\_TASK\_LOCK is required in SMP | FreeRTOS.h | /ScanAndSystemController/AppSw/Tricore/OS/FreeRTOS/include | line 442 | C/C++ Problem | | ctc E201: #error portRELEASE\_ISR\_LOCK is required in SMP | FreeRTOS.h | /ScanAndSystemController/AppSw/Tricore/OS/FreeRTOS/include | line 452 | C/C++ Problem | | ctc E201: #error portRELEASE\_TASK\_LOCK is required in SMP | FreeRTOS.h | /ScanAndSystemController/AppSw/Tricore/OS/FreeRTOS/include | line 432 | C/C++ Problem | | ctc E201: #error portSET\_INTERRUPT\_MASK is required in SMP | FreeRTOS.h | /ScanAndSystemController/AppSw/Tricore/OS/FreeRTOS/include | line 414 | C/C++ Problem | Thanks! ---
**Author:** ![Fresh](https://avatars.discourse-cdn.com/v4/letter/f/2acd7d/32.png) [@Fresh](https://forums.freertos.org/u/Fresh)\ **Post date:** [February 22, 2024, 8:12am UTC](https://forums.freertos.org/t/freertos-smp-with-infineon-aurix-tc3xx/19227/2 "2024-02-22T08:12:18Z")
@Chee2oo Thank you for your interesting in migrating to FreeRTOS v11 and using SMP scheduler. The missing port functions in your list are required by SMP scheduler. You can reference [this checklist](https://forums.freertos.org/t/smp-porting-checklist-a53-4-as-reference/14499/6) for creating a SMP port. Existing SMP port [RP2040](https://www.freertos.org/smp-demos-for-the-raspberry-pi-pico-board.html) and [XMOS](https://www.freertos.org/smp-demo-for-xmos-xcore-ai-explorer-board.html) can also be used as an example implementation. Please take a look and post further question here. ---
**Author:** ![kstribrn](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/kstribrn/32/2085_2.png) [@kstribrn](https://forums.freertos.org/u/kstribrn)\ **Post date:** [February 23, 2024, 6:37pm UTC](https://forums.freertos.org/t/freertos-smp-with-infineon-aurix-tc3xx/19227/3 "2024-02-23T18:37:14Z")
The [portmacro.h](https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/portable/ThirdParty/GCC/RP2040/include/portmacro.h) file will probably be most helpful to you. This file defines most of (if not all of) the macros you’re missing. ---
**Author:** ![go2sh](https://avatars.discourse-cdn.com/v4/letter/g/439d5e/32.png) [@go2sh](https://forums.freertos.org/u/go2sh)\ **Post date:** [December 10, 2024, 1:11pm UTC](https://forums.freertos.org/t/freertos-smp-with-infineon-aurix-tc3xx/19227/4 "2024-12-10T13:11:11Z")
Aurix MCUs are not really meant to be used in a SMP manor. A few things make it really difficult: - Part of the stack are contained in the context save areas, which are tightly linked to the core. It would make substantial overhead to swap them out for each task and CSAs which are not in tightly couple memory make function calls and interrupts really slow. If you pass tasks between cpu without dedicated CSA list, you can leak CSAs from one core to another and one might run out. - Aurix has no cache coherency. A SMP port with cache memory would always need to flush the data cache and maybe the program cache. - Aurix has a heterogeneous memory architecture. Depending where your memory and core are, you are getting different access latencies. My suggestion is to run freeRTOS in an AMP mode and run a dedicated freeRTOS instance on each core. Use message passing to communicate between each cores or a RPC framework. Place your code for a task in a sperate file to easily pass same between different instances.