FreeRTOS SMP on Coretex-R5F

[richard-damon]

@Dirk

There are two considerations：
1.We want to tap into the computing power of this platform as much as possible, so the SMP structure maybe a good way to achieve this.
2.We want to provide a platform so that the software development engineers do not need to consider which CPU core should the task be developed, they only need to develop the task software and determine the priority of tasks,and task scheduling is entrusted to SMP FreeRTOS.

The problem is that the hardware just doesn’t support that level of abstraction. The use of Tightly Coupled Memory doesn’t work in the concept of not caring which processor runs a task. A processor designed for that sort of operation would replace that TCM with a large cache, probably with 2 levels, and a perhaps a larger global memory.