# FreeRTOS ports for RISC-V for MicroChip PolarFire, PolarFire SoC, and Xilinx FPGAs?

**URL:** <https://forums.freertos.org/t/freertos-ports-for-risc-v-for-microchip-polarfire-polarfire-soc-and-xilinx-fpgas/23341>\
**Category:** Kernel\
**Created:** [July 1, 2025, 11:38pm UTC](https://forums.freertos.org/t/freertos-ports-for-risc-v-for-microchip-polarfire-polarfire-soc-and-xilinx-fpgas/23341 "2025-07-01T23:38:46Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![danielglasser](https://avatars.discourse-cdn.com/v4/letter/d/5daacb/32.png) [@danielglasser](https://forums.freertos.org/u/danielglasser)\
**Post date:** [July 1, 2025, 11:38pm UTC](https://forums.freertos.org/t/freertos-ports-for-risc-v-for-microchip-polarfire-polarfire-soc-and-xilinx-fpgas/23341/1 "2025-07-01T23:38:46Z")

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The number of RISC-V ports is small and the variety of implementations of the architecture is getting larger, and the FPGA vendors seem to be dropping support for FreeRTOS without providing much of a viable alternative for their soft IP cores. For Microchip, this is the “mi-v” that can be configured as rv32imc, and soon rv32imac, and possibly rv32imacfd (I saw an announcement of a new version of RISC-V soft core from Microchip coming out soon/now). For Xilinx, the variety of RISC-V configurations seems to be larger, offering both 32 and 64-bit soft cores and a wide variety of extensions.

There are some older Microchip ports I’ve found, but none of them seem to be maintained or listed in the “Partner” or “Community” supported ports. I tried to modify a few of the GCC RISC-V ports specific to a particular chip vendor’s RISC-V implementation, but so far am having little luck with context switching. The tools I currently have available do not support OS Aware debugging, so it may take a while.

RISC-V is becoming more available and appearing in a lot of places. The variety of flavors is a bit confusing.

A pair of ports (one each for 64 and 32 bit varieties) that had configurable (via header-file) support for the common extensions (A, M, C, F, D) and privilege architecture (Machine, User, Supervisor) instruction set support would be very valuable in keeping FreeRTOS a good option for new development.

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**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\
**Post date:** [July 7, 2025, 4:53am UTC](https://forums.freertos.org/t/freertos-ports-for-risc-v-for-microchip-polarfire-polarfire-soc-and-xilinx-fpgas/23341/2 "2025-07-07T04:53:29Z")

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Thank you for your suggestion, @danielglasser! Would you mind opening a GitHub issue to describe your proposal in detail? In case you decide to implement it, we always welcome contributions 🙂