# FreeRTOS + GCC + Cortex A9 interrupt float value corruption and resolution - need some insight **URL:** \ **Category:** Kernel\ **Created:** [January 23, 2022, 5:50am UTC](https://forums.freertos.org/t/freertos-gcc-cortex-a9-interrupt-float-value-corruption-and-resolution-need-some-insight/14279 "2022-01-23T05:50:20Z")\ **Posts on this page:** 1\ **Showing post:** 19
**Author:** ![Loustiic](https://avatars.discourse-cdn.com/v4/letter/l/ea5d25/32.png) [@Loustiic](https://forums.freertos.org/u/Loustiic)\ **Post date:** [June 29, 2026, 9:30am UTC](https://forums.freertos.org/t/freertos-gcc-cortex-a9-interrupt-float-value-corruption-and-resolution-need-some-insight/14279/19 "2026-06-29T09:30:37Z")
Sorry for the late reply, I encountered the same problem on a Zynq 7020, and noticed I was not the only one. So I opened a pull request for the Cortex A9 to adapt the work done on Cortex R5 and MPSOC ( [Zynq Ultrascale MPSoC task floating point corruption - #30 by wat](https://forums.freertos.org/t/zynq-ultrascale-mpsoc-task-floating-point-corruption/9121/30) ) : [Conditionally save FPU context in IRQ, and preserve vApplicationFPUSa… by Loustiic · Pull Request #1429 · FreeRTOS/FreeRTOS-Kernel · GitHub](https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/1429) . I think it is still relevant because my initial understanding was that **configUSE\_TASK\_FPU\_SUPPORT =1 or 2** would solve my issue, but I had to patch Xilinx’s BSP to solve the issue. I think this patch might be a idea for this reason (and the fact that it homogenize **configUSE\_TASK\_FPU\_SUPPORT** behavior with respect to other architectures) Thanks! --- _[View the full topic](https://forums.freertos.org/t/freertos-gcc-cortex-a9-interrupt-float-value-corruption-and-resolution-need-some-insight/14279)._