# Cortex R5F Peripheral Base Address **URL:** \ **Category:** Percepio\ **Tags:** tracealyzer\ **Created:** [August 23, 2022, 10:35am UTC](https://forums.freertos.org/t/cortex-r5f-peripheral-base-address/15672 "2022-08-23T10:35:18Z")\ **Posts on this page:** 7\ **Page:** 1
**Author:** ![SteveB](https://avatars.discourse-cdn.com/v4/letter/s/ea666f/32.png) [@SteveB](https://forums.freertos.org/u/SteveB)\ **Post date:** [August 23, 2022, 10:35am UTC](https://forums.freertos.org/t/cortex-r5f-peripheral-base-address/15672/1 "2022-08-23T10:35:18Z")
I’m investigating using traceanalyzer with the Cortex R5F processors on the TI Jacinto platform. Does anyone know where to find the Peripheral base address required to configure the hardware port to enable the analyser to access the counter registers? ---
**Author:** ![SteveB](https://avatars.discourse-cdn.com/v4/letter/s/ea666f/32.png) [@SteveB](https://forums.freertos.org/u/SteveB)\ **Post date:** [August 23, 2022, 4:22pm UTC](https://forums.freertos.org/t/cortex-r5f-peripheral-base-address/15672/2 "2022-08-23T16:22:52Z")
Currently I’m finding the comment in trcHardwarePort.h ‘_but should work with all Cortex-A and R processors assuming that TRC\_CA9\_MPCORE\_PERIPHERAL\_BASE\_ADDRESS is set accordingly._’ to be somewhat misleading. As far as I can private timer of the A9 referred to by the registers does not exist in the Cortex-R processors. ---
**Author:** ![kristoffer\_percepio](https://avatars.discourse-cdn.com/v4/letter/k/a9adbd/32.png) [@kristoffer\_percepio](https://forums.freertos.org/u/kristoffer_percepio)\ **Post date:** [August 24, 2022, 6:25am UTC](https://forums.freertos.org/t/cortex-r5f-peripheral-base-address/15672/3 "2022-08-24T06:25:45Z")
You might be correct about the comment that might be a little bit misleading. I am not familiar with this TI platform so I can’t provide details to implement the HW port for it. But in general, there are two things that must be done. First, you need a time source, normally a hardware timer. The below defines should be configured: #define TRC\_HWTC\_TYPE #define TRC\_HWTC\_COUNT #define TRC\_HWTC\_PERIOD #define TRC\_HWTC\_DIVISOR #define TRC\_HWTC\_FREQ\_HZ Second is the critical sections. There are a few HW ports for Cortex-A9 and Cortex-R5 that use the same implementation of the critical section. So maybe it can be reused. There is a blog post with some more details here: > **[Developer Blog: Adapting Tracealyzer to the Nios II soft-core CPU - Percepio AB](https://percepio.com/2020/05/06/devblog-adapting-tracealyzer-nios-ii/)** > > It is quite simple to extend Percepio's trace recorder library to work with a new processor. Today's article shows how to do it, using an Intel Nios II soft-core CPU as an example. ---
**Author:** ![SteveB](https://avatars.discourse-cdn.com/v4/letter/s/ea666f/32.png) [@SteveB](https://forums.freertos.org/u/SteveB)\ **Post date:** [August 24, 2022, 8:47am UTC](https://forums.freertos.org/t/cortex-r5f-peripheral-base-address/15672/4 "2022-08-24T08:47:34Z")
Thanks Kristoffer. That clarifies the situation. I think the TI PDK and documentation provide all the required information, with the possible exception of the divisor/prescaler. ---
**Author:** ![Fnx\_QT](https://avatars.discourse-cdn.com/v4/letter/f/b4bc9f/32.png) [@Fnx\_QT](https://forums.freertos.org/u/Fnx_QT)\ **Post date:** [October 26, 2022, 12:12pm UTC](https://forums.freertos.org/t/cortex-r5f-peripheral-base-address/15672/5 "2022-10-26T12:12:46Z")
Hello @SteveB, I’m basically recreating the same setup as you except its for the TI AM64x platform, also based on a Cortex-R5F. Did you finally achieved something working ? I have a hard time figuring out where is the processor header file in TI’s case (is it necessary when not using a Cortex-M ?) But more importantly I absolutely can’t find any info about the peripheral base address. Could you show me where you find it in the TI Jacinto PDK? Many thanks. ---
**Author:** ![SteveB](https://avatars.discourse-cdn.com/v4/letter/s/ea666f/32.png) [@SteveB](https://forums.freertos.org/u/SteveB)\ **Post date:** [October 27, 2022, 9:29pm UTC](https://forums.freertos.org/t/cortex-r5f-peripheral-base-address/15672/6 "2022-10-27T21:29:04Z")
Hi @Fnx_QT, Sorry, I didn’t end up taking this any further. The approach I would take is to ignore the comments in trcHardwarePort.h with reference to Peripheral\_base\_address and focus on the example linked by kristoffer\_percepio. For the listed #define on the Jacinto/J721e I’d be looking at #define TRC\_HWTC\_TYPE TRC\_OS\_TIMER\_INCR #define TRC\_HWTC\_COUNT ‘function from the processor port’, e.g. uxPortGetTimeInUsec() #define TRC\_HWTC\_PERIOD 2^32 - Counter is an unsigned 32bit variable #define TRC\_HWTC\_DIVISOR Don’t know #define TRC\_HWTC\_FREQ\_HZ 1000000 - based on a 1us timer The critical section functions you should fine in the port (portmacro.h), e.g. TRACE\_ALLOC\_CRITICAL\_SECTION() Not sure - A local variable declaration for storing the interrupt status. TRACE\_ENTER\_CRITICAL\_SECTION() vPortEnterCritical() TRACE\_EXIT\_CRITICAL\_SECTION() vPortExitCritical() All a bit hypothetical I’m afraid. Would be interested to know how you get on. Cheers Steve ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [November 13, 2022, 9:10am UTC](https://forums.freertos.org/t/cortex-r5f-peripheral-base-address/15672/7 "2022-11-13T09:10:32Z")
Thanks for your response @SteveB.