# Cortex M7 Triggering Hard fault randomly at different places

**URL:** <https://forums.freertos.org/t/cortex-m7-triggering-hard-fault-randomly-at-different-places/13177>\
**Category:** ARM\
**Created:** [August 6, 2021, 3:51pm UTC](https://forums.freertos.org/t/cortex-m7-triggering-hard-fault-randomly-at-different-places/13177 "2021-08-06T15:51:06Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![shinoysathyan](https://avatars.discourse-cdn.com/v4/letter/s/dfb087/32.png) [@shinoysathyan](https://forums.freertos.org/u/shinoysathyan)\
**Post date:** [August 6, 2021, 3:51pm UTC](https://forums.freertos.org/t/cortex-m7-triggering-hard-fault-randomly-at-different-places/13177/1 "2021-08-06T15:51:07Z")

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Hello,

We have a strange problem with CORTEX M7 (STM32F765) running FreeRTOS version 7.3.0

Hard faults are getting triggered randomly at different places in software.  
Most of the time It is the FreeRTOS code that is triggering the fault (observation from call stack)

No issue with interrupt priority settings and no stack overflow observed.

Listed below are some of the STM32f765 fault flags that are getting set when faults are triggered.  
INVSTATE, PRECISERR, IMPRECISERR, BFARVALID, BFAR, UNALIGNED, INVALIDINSTRUCTION

Any pointers on what can trigger this kind of system behavior?

Thanks,  
Shinoy

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**Author:** ![rtel](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/rtel/32/31_2.png) [@rtel](https://forums.freertos.org/u/rtel)\
**Post date:** [August 6, 2021, 10:10pm UTC](https://forums.freertos.org/t/cortex-m7-triggering-hard-fault-randomly-at-different-places/13177/2 "2021-08-06T22:10:47Z")

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I don’t think V7.3.0 supports the M7.

History:

- We created a Cortex-M4F port that covered the subset of the Cortex-M specification actually implemented by M4 devices.
- Later the M7 was launched, at which time we updated the M4 port so it could also be used with the M7. That required additional memory barriers, etc.
- r0p1 revision cores of the M7 contain an errata that required a specific FreeRTOS port that worked around the errata. So now if you use an r0p1 core you need to use this port, [FreeRTOS-Kernel/portable/GCC/ARM\_CM7/r0p1 at main · FreeRTOS/FreeRTOS-Kernel · GitHub](https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/main/portable/GCC/ARM_CM7/r0p1) otherwise you can use the Cortex-M4 port, but only ports since M7 support was added otherwise you are likely to get the symptoms you describe (missing memory barriers will create intermittent errors that will depend on clock speeds and whatever else the device is doing a the time).

History file indicates M7 support was added in V8.2.1, which was when the first production chip was available [FreeRTOS-Kernel/History.txt at main · FreeRTOS/FreeRTOS-Kernel · GitHub](https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/History.txt#L686)

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<div class="post-metadata">

**Author:** ![shinoysathyan](https://avatars.discourse-cdn.com/v4/letter/s/dfb087/32.png) [@shinoysathyan](https://forums.freertos.org/u/shinoysathyan)\
**Post date:** [August 16, 2021, 5:48pm UTC](https://forums.freertos.org/t/cortex-m7-triggering-hard-fault-randomly-at-different-places/13177/3 "2021-08-16T17:48:48Z")

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Thanks Richard Barry.

We tried migrating to 10.2.0 version of FreeRTOS but the problem still persists.  
Here is the Interrupt priority configuration that we are using. Is this fine?

Interrupts are assigned priority from 11 to 15

configKERNEL\_INTERRUPT\_PRIORITY 255  
configMAX\_SYSCALL\_INTERRUPT\_PRIORITY 175 // 0xAF

SysTick\_IRQn 15  
OTG\_FS\_IRQn 11  
ETH\_IRQn 13  
EXTI0\_IRQn 13  
EXTI1\_IRQn 13  
EXTI4\_IRQn 13  
EXTI9\_5\_IRQn 13  
USART1\_IRQn 13  
USART2\_IRQn 13  
USART3\_IRQn 13  
UART5\_IRQn 13  
UART4\_IRQn 13  
UART7\_IRQn 13

Thanks  
Shinoy