# Cortex-M MPU ports delay high priority ISRs **URL:** \ **Category:** Kernel\ **Created:** [August 11, 2026, 6:02pm UTC](https://forums.freertos.org/t/cortex-m-mpu-ports-delay-high-priority-isrs/25115 "2026-08-11T18:02:24Z")\ **Posts on this page:** 4\ **Page:** 1
**Author:** ![dbrunner4](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/dbrunner4/32/6393_2.png) [@dbrunner4](https://forums.freertos.org/u/dbrunner4)\ **Post date:** [August 11, 2026, 6:02pm UTC](https://forums.freertos.org/t/cortex-m-mpu-ports-delay-high-priority-isrs/25115/1 "2026-08-11T18:02:24Z")
The documentation says that interrupts above `configMAX_SYSCALL_INTERRUPT_PRIORITY` are not delayed by the kernel. (Among other places, in the FreeRTOS customization page’s `configKERNEL_INTERRUPT_PRIORITY` section: “Interrupts with priority above `configMAX_SYSCALL_INTERRUPT_PRIORITY` are never delayed by the RTOS kernel activity.” However, the Cortex-M MPU ports don’t meet that promise as of kernel 11.3.0. `xPortStartScheduler()` writes `SHPR2 = 0`, making SVCall the highest-priority exception in the system. With the v2 MPU wrappers, every FreeRTOS API call made by an unprivileged task enters _and_ exits the kernel through SVC. While those handlers run at priority 0, **every** interrupt is blocked — including application interrupts above `configMAX_SYSCALL_INTERRUPT_PRIORITY` whose timing the kernel promises not to affect. I was able to fix this on my system (STM32H7A3, Cortex-M7 r1p1 @ 280 MHz, GCC, mpu\_wrappers\_v2, 16 MPU regions, all tasks unprivileged, 4 priority bits,`configMAX_SYSCALL_INTERRUPT_PRIORITY` at NVIC level 5, `configSVCALL_INTERRUPT_PRIORITY` at level 4) by making the SVCall priority configurable: a new `configSVCALL_INTERRUPT_PRIORITY`, written to SHPR2 in place of the hardcoded 0. I placed this below my time-critical ISR band, so that those ISRs now preempt SVC dispatch. The SVCall priority has to be numerically lower than `configMAX_SYSCALL_INTERRUPT_PRIORITY` so that the scheduler startup works. I’m curious to see what everyone thinks of this and if I’ve missed anything. ---
**Author:** ![jefftenney](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/jefftenney/32/1314_2.png) [@jefftenney](https://forums.freertos.org/u/jefftenney)\ **Post date:** [August 12, 2026, 1:26am UTC](https://forums.freertos.org/t/cortex-m-mpu-ports-delay-high-priority-isrs/25115/2 "2026-08-12T01:26:47Z")
Hi @dbrunner4 and welcome to the forum. I think you are right. [This discussion](https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/832#discussion_r1372103866) from a few years ago went a little too fast, and a contributor who shall remain nameless later made [this commit](https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/832/changes/2e6494b691e4904fa3cbf4addaa06b0b5da5ed97) which changed the setting in SHPR2. I like that the commit moved the setting to a more logical place, but I don’t like that it is set to zero. It should probably be set to [the original value](https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/869f78e2b080f3d3b5550f26747c3c5b8b724a66/portable/GCC/ARM_CM4_MPU/port.c#L102): `#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL` I’d be glad to submit the PR if it helps, but I can’t get to it until Monday. Alternatively, you could submit the PR if you want to. ---
**Author:** ![aggarg](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/aggarg/32/4245_2.png) [@aggarg](https://forums.freertos.org/u/aggarg)\ **Post date:** [August 13, 2026, 5:49am UTC](https://forums.freertos.org/t/cortex-m-mpu-ports-delay-high-priority-isrs/25115/3 "2026-08-13T05:49:02Z")
> [@jefftenney](#): > > I’d be glad to submit the PR if it helps Thank you @jefftenney! Please raise the PR. ---
**Author:** ![jefftenney](https://d3iykfbgfh8zhg.cloudfront.net/user_avatar/forums.freertos.org/jefftenney/32/1314_2.png) [@jefftenney](https://forums.freertos.org/u/jefftenney)\ **Post date:** [September 25, 2026, 8:21pm UTC](https://forums.freertos.org/t/cortex-m-mpu-ports-delay-high-priority-isrs/25115/4 "2026-09-25T20:21:16Z")
Just closing the loop here. [PR #1470](https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/1470) was merged. It restores the original behavior for ARMv7-M MPU ports from before v11.0.0. Specifically, it reduces the SVC priority from 0 (the maximum priority) back to `configMAX_SYSCALL_INTERRUPT_PRIORITY - 1`. A separate PR ([#1481](https://github.com/FreeRTOS/FreeRTOS-Kernel/pull/1481)) is under consideration to apply a similar improvement to the ARMv8-M ports. The ARMv8-M ports have used SVC priority 0 (the maximum priority) from the beginning.