Context Saving - Restoring with Cortex M3

damiennone wrote on Tuesday, March 06, 2012:

Hi all,

Recently , I started using the Cortex M3 GCC port.

My question is connected to the context saving - restoring during interrupt servicing :

According to the Cortex M3 architecture and my understanding: Only register from R4 until R11 has to be saved. Other registers are automatically stacked - unstacked by the processor and the NVIC before - after Interrupt routine execution.

I started my project using the Stellaris CORTEX_LM3Sxxxx_Eclipse demo :

I found the piece of code doing the job for the FreeRTOS kernel scheduling systick timer interrupt, but for other interrupt function used by the demo  (void vT2InterruptHandler( void ) for example),

I have not been able to find the context saving - restoring code or any kind of key word which could tell to the compiler the present function is an interrupt function (__attribute__ ((interrupt)))

How this context saving - restoring has to be done for handling ISR with FreeRTOS - Cortex M3 or if not necessary, why ?

Thanks for any explaination


From my understanding,

rtel wrote on Tuesday, March 06, 2012:

Context saving and restoring is only performed from the PendSV interrupt.  If an application interrupt wants to force a context switch, it pends the PendSV interrupt (FreeRTOS provides macros to do this, the application does not have to write to the core directly), and the PendSV interrupt executes when all higher priority interrupts (potentially nested) have executed.

Look at the implementation of the PendSV interrupt in port.c.


damiennone wrote on Tuesday, March 06, 2012:

Hi Richard,

Thanks for reply, and thanks for helping a no specialist of Cortex M3 architecture

You have right, PendSV interrupt is implemented with a “full” saving of register (R4-R11).

Now, supposing any different interrupt source (Tim2 and Tim3, as used in the demo CORTEX_LM3Sxxxx_Eclipse, I would like to add my interrupt for RS232 Comm) :

Do I have to take care about copy - restoring these register (R4-R11) when branching - leaving  interrupt ?

I suppose Yes but I’m surprised to not find this code in the demo.
If I’m wrong, what is the reason ?

My previous experience with the STR91X port, from my memory ->  was a piece of code in assembler doing this copy - restoration of all Register before branching - returning the interruption.

Thanks in advance.


davedoors wrote on Tuesday, March 06, 2012:

You don’t have to do anything except write standard C code, the kernel takes care of everything. Context switched only ever happen in the PendSV handler, never anywhere else.

Look at the interrupt service routine section of a documentation page related to a Cortex demo.