I think it wants to set the edge-triggered bit in the appropriate Interrupt Interrupt Configuration Register, but it looks like it is OR’ing the edge-triggered bit with the contents of the Interrupt Controller Type Register at GCDistributorAddress+4 (e.g. for “vector” 29).
This makes no sense to me. Am I missing something? Why does it read (puxGICDistributorAddress + ulBank16) and OR the edge-triggered bit into that value?
There is not (yet) an official Real Time Engineers ltd maintained Cortex-A9 port. Did you get your code from the FreeRTOS Interactive site? If so, please let me know which post the code came from and I may be able to ping the authour for a reply.
I have convinced myself that this is a bug in the code, but I don’t think it matters for the Cortex-A9 MPCore, as ICDICR0 and ICDICR1 are read-only registers. Different implementations, e.g. single Cortex-A9 with a GIC, might have a problem.