ARM CM3: use a general register for MSR

anonymous wrote on Sunday, March 22, 2009:

The code for portSET_INTERRUPT_MASK() and portCLEAR_INTERRUPT_MASK() of the GCC ARM CM3 port hardcodes the use of the r0 register as the intermediate value to use as "msr basepri, r0". Any general register can be used here, and sometimes letting GCC choose leads to a shorter and faster code.

By using respectively

  __asm volatile("msr basepri,%0" : : "r"(configMAX_SYSCALL_INTERRUPT_PRIORITY));


  _asm  volatile("msr basepri,%0" : : "r"(0));

we can only get better code: in the worst case, we get the equivalent two instructions, in the best case, the compiler knows that rconfigMAX_SYSCALL_INTERRUPT_PRIORITY/0 is already loaded into a register at this point and will use it. Also, it decreases the register pressure on r0 by allowing the use of a different register should it lead to a better code.

For example, vPortExitCritical will then get compiled as

    1488:       4a03            ldr     r2, [pc, #12]   (1498 <vPortExitCritical+0x10>)
    148a:       6813            ldr     r3, [r2, #0]
    148c:       3b01            subs    r3, #1
    148e:       6013            str     r3, [r2, #0]
    1490:       b90b            cbnz    r3, 1496 <vPortExitCritical+0xe>
    1492:       f383 8811       msr     BASEPRI, r3
    1496:       4770            bx      lr

Here, at address 1492, the compiler knows that r3 (which contains the uxCriticalNesting value) is necessarily 0 and uses it instead of reloading the constant 0 into another register.

rtel wrote on Sunday, March 22, 2009:

Very good post - thanks for sharing.


anonymous wrote on Tuesday, March 24, 2009:


any chance to get this change applied to the SVN repository?

(I’m already using it in my local copy, I just want to make sure it doesn’t get forgotten)


rtel wrote on Tuesday, March 24, 2009:

Can you add it to the feature request tracker in SourceForge please.  That way it won’t get forgotten.