AArch64 single-core FreeRTOS mutex and ARM exclusive instructions

[H_a_r_i_n_i]

Hi,

I am working with a single-core FreeRTOS application on an ARM Cortex-A55 using AArch64.

I traced xSemaphoreTake() → xQueueSemaphoreTake() and inspected the generated AArch64 assembly.

The mutex acquisition is performed inside a FreeRTOS critical section. In the generated assembly, I see:

MSR DAIFSet, #3
…
LDR
SUB
STR
…
MSR DAIFClr, #3

I do not see ARM exclusive instructions such as LDXR/STXR or LDAXR/STLXR in the mutex acquisition path.

I would like to confirm whether this is the expected behavior for a single-core AArch64 FreeRTOS configuration.

In particular:

1. Is the critical-section approach with interrupt masking the expected way to protect the mutex state on a single-core AArch64 system?
2. In which FreeRTOS configurations would ARM exclusive instructions such as LDXR/STXR normally be required?
3. Are they primarily relevant to SMP/inter-core synchronization?

I am trying to understand whether the behavior I observed is expected for the single-core AArch64 FreeRTOS design.

Thanks.

[aggarg (Gaurav Aggarwal)]

@H_a_r_i_n_i

1. Is the critical-section approach with interrupt masking the expected way to protect the mutex state on a single-core AArch64 system?

Yes, this is expected.

@H_a_r_i_n_i

2. In which FreeRTOS configurations would ARM exclusive instructions such as LDXR/STXR normally be required?
3. Are they primarily relevant to SMP/inter-core synchronization?

Yes, that is one way to implement spin locks in SMP used for cross-core synchronization. Example: FreeRTOS-Kernel/portable/GCC/ARM_CR82/port.c at main · FreeRTOS/FreeRTOS-Kernel · GitHub.

@H_a_r_i_n_i

I am trying to understand whether the behavior I observed is expected for the single-core AArch64 FreeRTOS design.

It is expected behavior. Are you facing any issue?